Ticket #11051: xf86-video-ati-18.0.1-upstream_patches-2.patch

xf86-video-ati-18.0.1

@@ -109 +109 @@
 
     device_iter = pci_slot_match_iterator_create(NULL);
 
-    while ((device = pci_device_next(device_iter)) != NULL) {
+    while ((device = pci_device_next(device_iter))) {
         if (xf86IsPrimaryPci(device))
             break;
     }
@@ -128 +128 @@
 
     device_iter = pci_slot_match_iterator_create(NULL);
 
-    while ((device = pci_device_next(device_iter)) != NULL) {
+    while ((device = pci_device_next(device_iter))) {
         if (device->vendor_id == PCI_VENDOR_ATI) {
             if (count == index)
                 return device;

src/drmmode_display.c

@@ -100 +100 @@
 }
 
 
-/* Wait for the boolean condition to be FALSE */
-#define drmmode_crtc_wait_pending_event(drmmode_crtc, fd, condition) \
-        do {} while ((condition) && \
-                     drmHandleEvent(fd, &drmmode_crtc->drmmode->event_context) \
-                     > 0);
-
-
 static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
                                           int width, int height,
                                           int depth, int bpp,
                                           int pitch,
-                                          struct radeon_bo *bo, struct radeon_surface *psurf)
+                                          struct radeon_buffer *bo)
 {
         RADEONInfoPtr info = RADEONPTR(pScrn);
         ScreenPtr pScreen = pScrn->pScreen;
         PixmapPtr pixmap;
-        struct radeon_surface *surface;
-        uint32_t tiling;
 
         pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth,
                                           RADEON_CREATE_PIXMAP_SCANOUT);
@@ -135 +126 @@
         if (!radeon_set_pixmap_bo(pixmap, bo))
                 goto fail;
 
-        if (info->ChipFamily >= CHIP_FAMILY_R600) {
-                surface = radeon_get_pixmap_surface(pixmap);
-                if (surface && psurf) 
-                        *surface = *psurf;
-                else if (surface) {
-                        memset(surface, 0, sizeof(struct radeon_surface));
-                        surface->npix_x = width;
-                        surface->npix_y = height;
-                        surface->npix_z = 1;
-                        surface->blk_w = 1;
-                        surface->blk_h = 1;
-                        surface->blk_d = 1;
-                        surface->array_size = 1;
-                        surface->last_level = 0;
-                        surface->bpe = bpp / 8;
-                        surface->nsamples = 1;
-                        surface->flags = RADEON_SURF_SCANOUT;
-                        /* we are requiring a recent enough libdrm version */
-                        surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-                        surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-                        surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-                        tiling = radeon_get_pixmap_tiling_flags(pixmap);
-                        if (tiling & RADEON_TILING_MICRO) {
-                                surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-                                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-                        }
-                        if (tiling & RADEON_TILING_MACRO) {
-                                surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-                                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-                        }
-                        if (radeon_surface_best(info->surf_man, surface)) {
-                                goto fail;
-                        }
-                        if (radeon_surface_init(info->surf_man, surface)) {
-                                goto fail;
-                        }
-                }
+        if (info->surf_man && !info->use_glamor) {
+                struct radeon_surface *surface = radeon_get_pixmap_surface(pixmap);
+
+                if (!radeon_surface_initialize(info, surface, width, height, bpp / 8,
+                                               radeon_get_pixmap_tiling_flags(pixmap), 0))
+                        goto fail;
         }
 
         if (!info->use_glamor ||
-            radeon_glamor_create_textured_pixmap(pixmap,
-                                                 radeon_get_pixmap_private(pixmap)))
+            radeon_glamor_create_textured_pixmap(pixmap, bo))
                 return pixmap;
 
 fail:
@@ -340 +299 @@
         if (drmmode_crtc->dpms_mode == DPMSModeOn && mode != DPMSModeOn) {
                 uint32_t seq;
 
-                drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd,
-                                                drmmode_crtc->flip_pending);
+                radeon_drm_wait_pending_flip(crtc);
 
                 /*
                  * On->Off transition: record the last vblank time,
@@ -366 +324 @@
                                 nominal_frame_rate /= pix_in_frame;
                         drmmode_crtc->dpms_last_fps = nominal_frame_rate;
                 }
+
+                drmmode_crtc->dpms_mode = mode;
+                radeon_drm_queue_handle_deferred(crtc);
         } else if (drmmode_crtc->dpms_mode != DPMSModeOn && mode == DPMSModeOn) {
                 /*
                  * Off->On transition: calculate and accumulate the
@@ -383 +344 @@
                         drmmode_crtc->interpolated_vblanks += delta_seq;
 
                 }
+
+                drmmode_crtc->dpms_mode = DPMSModeOn;
         }
-        drmmode_crtc->dpms_mode = mode;
 }
 
 static void
@@ -395 +357 @@
 
         /* Disable unused CRTCs */
         if (!crtc->enabled || mode != DPMSModeOn) {
-                drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd,
-                                                drmmode_crtc->flip_pending);
+                drmmode_do_crtc_dpms(crtc, DPMSModeOff);
                 drmModeSetCrtc(pRADEONEnt->fd, drmmode_crtc->mode_crtc->crtc_id,
                                0, 0, 0, NULL, 0, NULL);
                 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL);
@@ -412 +373 @@
         RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
         RADEONInfoPtr info = RADEONPTR(pScrn);
         PixmapPtr pixmap = info->fbcon_pixmap;
-        struct radeon_bo *bo;
+        struct radeon_buffer *bo;
         drmModeFBPtr fbcon;
         struct drm_gem_flink flink;
 
@@ -420 +381 @@
             return pixmap;
 
         fbcon = drmModeGetFB(pRADEONEnt->fd, fbcon_id);
-        if (fbcon == NULL)
+        if (!fbcon)
                 return NULL;
 
         if (fbcon->depth != pScrn->depth ||
@@ -435 +396 @@
                 goto out_free_fb;
         }
 
-        bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
-        if (bo == NULL) {
+        bo = calloc(1, sizeof(struct radeon_buffer));
+        if (!bo) {
                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-                           "Couldn't allocate bo for fbcon handle\n");
+                           "Couldn't allocate BO for fbcon handle\n");
+                goto out_free_fb;
+        }
+        bo->ref_count = 1;
+
+        bo->bo.radeon = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
+        if (!bo) {
+                xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+                           "Couldn't open BO for fbcon handle\n");
                 goto out_free_fb;
         }
 
         pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
                                           fbcon->depth, fbcon->bpp, fbcon->pitch,
-                                          bo, NULL);
+                                          bo);
         info->fbcon_pixmap = pixmap;
-        radeon_bo_unref(bo);
+        radeon_buffer_unref(&bo);
 out_free_fb:
         drmModeFreeFB(fbcon);
         return pixmap;
@@ -460 +429 @@
         /* XXX: The current GPUVM support in the kernel doesn't allow removing
          * the virtual address range for this BO, so we need to keep around
          * the pixmap to avoid breaking glamor with GPUVM
+         *
+         * Similarly, need to keep around the pixmap with current glamor, to
+         * avoid issues due to a GEM handle lifetime conflict between us and
+         * Mesa
          */
-        if (info->use_glamor && info->ChipFamily >= CHIP_FAMILY_CAYMAN)
+        if (info->use_glamor &&
+            (info->ChipFamily >= CHIP_FAMILY_CAYMAN ||
+             xorgGetVersion() >= XORG_VERSION_NUMERIC(1,19,99,1,0)))
                 return;
 
         if (info->fbcon_pixmap)
@@ -529 +504 @@
                 scanout->pixmap = NULL;
         }
 
-        if (scanout->bo) {
-                radeon_bo_unmap(scanout->bo);
-                radeon_bo_unref(scanout->bo);
-                scanout->bo = NULL;
-        }
+        radeon_buffer_unref(&scanout->bo);
 }
 
 void
@@ -581 +552 @@
                                                  width, height,
                                                  pScrn->depth,
                                                  pScrn->bitsPerPixel,
-                                                 pitch, scanout->bo, NULL);
+                                                 pitch, scanout->bo);
         if (!scanout->pixmap) {
                 ErrorF("failed to create CRTC scanout pixmap\n");
                 goto error;
@@ -693 +664 @@
         Bool ret;
 
 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,15,99,903,0)
-        if (crtc->transformPresent || crtc->rotation != RR_Rotate_0)
-            crtc->driverIsPerformingTransform = XF86DriverTransformOutput;
-        else
-            crtc->driverIsPerformingTransform = XF86DriverTransformNone;
+        crtc->driverIsPerformingTransform = XF86DriverTransformOutput;
 #else
         crtc->driverIsPerformingTransform = !crtc->transformPresent &&
-                crtc->rotation != RR_Rotate_0 &&
                 (crtc->rotation & 0xf) == RR_Rotate_0;
 #endif
 
@@ -759 +726 @@
                                           gc, 0, 0, mode->HDisplay, mode->VDisplay,
                                           0, 0);
                         FreeScratchGC(gc);
-                        radeon_cs_flush_indirect(scrn);
-                        radeon_bo_wait(drmmode_crtc->scanout[0].bo);
+                        radeon_finish(scrn, drmmode_crtc->scanout[0].bo);
                 }
         }
 
@@ -790 +756 @@
         if (drmmode_crtc->scanout[scanout_id].pixmap &&
             (!drmmode_crtc->tear_free ||
              drmmode_crtc->scanout[scanout_id ^ 1].pixmap)) {
-                RegionPtr region;
-                BoxPtr box;
+                BoxRec extents = { .x1 = 0, .y1 = 0,
+                                   .x2 = scrn->virtualX, .y2 = scrn->virtualY };
 
                 if (!drmmode_crtc->scanout_damage) {
                         drmmode_crtc->scanout_damage =
@@ -803 +769 @@
                                        drmmode_crtc->scanout_damage);
                 }
 
-                region = DamageRegion(drmmode_crtc->scanout_damage);
-                RegionUninit(region);
-                region->data = NULL;
-                box = RegionExtents(region);
-                box->x1 = 0;
-                box->y1 = 0;
-                box->x2 = max(box->x2, scrn->virtualX);
-                box->y2 = max(box->y2, scrn->virtualY);
-
                 *fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap);
                 *x = *y = 0;
 
                 radeon_scanout_do_update(crtc, scanout_id,
                                          screen->GetWindowPixmap(screen->root),
-                                         *box);
-                radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
+                                         extents);
+                RegionEmpty(DamageRegion(drmmode_crtc->scanout_damage));
+                radeon_finish(scrn, drmmode_crtc->scanout[scanout_id].bo);
         }
 }
 
@@ -922 +880 @@
                 drmmode_crtc_update_tear_free(crtc);
                 if (drmmode_crtc->tear_free)
                         scanout_id = drmmode_crtc->scanout_id;
-
-                drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red, crtc->gamma_green,
-                                          crtc->gamma_blue, crtc->gamma_size);
+                else
+                        drmmode_crtc->scanout_id = 0;
 
                 if (drmmode_crtc->prime_scanout_pixmap) {
                         drmmode_crtc_prime_scanout_update(crtc, mode, scanout_id,
@@ -947 +904 @@
                         fb = radeon_fb_create(pScrn, pRADEONEnt->fd,
                                               pScrn->virtualX, pScrn->virtualY,
                                               pScrn->displayWidth * info->pixel_bytes,
-                                              info->front_bo->handle);
+                                              info->front_buffer->bo.radeon->handle);
                         /* Prevent refcnt of ad-hoc FBs from reaching 2 */
                         drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL);
                         drmmode_crtc->fb = fb;
@@ -957 +914 @@
                         goto done;
                 }
 
-                drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd,
-                                                drmmode_crtc->flip_pending);
+                radeon_drm_wait_pending_flip(crtc);
 
                 if (!drmmode_set_mode(crtc, fb, mode, x, y))
                         goto done;
@@ -1010 +966 @@
 
                 if (drmmode_crtc->scanout[scanout_id].pixmap &&
                     fb != radeon_pixmap_get_fb(drmmode_crtc->
-                                               scanout[scanout_id].pixmap))
+                                               scanout[scanout_id].pixmap)) {
+                        radeon_drm_abort_entry(drmmode_crtc->scanout_update_pending);
+                        drmmode_crtc->scanout_update_pending = 0;
                         drmmode_crtc_scanout_free(drmmode_crtc);
-                else if (!drmmode_crtc->tear_free) {
+                } else if (!drmmode_crtc->tear_free) {
                         drmmode_crtc_scanout_destroy(drmmode,
                                                      &drmmode_crtc->scanout[1]);
                 }
         }
 
+        radeon_drm_queue_handle_deferred(crtc);
         return ret;
 }
 
@@ -1398 +1357 @@
         RADEONInfoPtr info = RADEONPTR(pScrn);
 
         crtc = xf86CrtcCreate(pScrn, &info->drmmode_crtc_funcs);
-        if (crtc == NULL)
+        if (!crtc)
                 return 0;
 
         drmmode_crtc = xnfcalloc(sizeof(drmmode_crtc_private_rec), 1);
@@ -1680 +1639 @@
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(output->scrn);
     drmModePropertyPtr drmmode_prop, tearfree_prop;
     int i, j, err;
+    Atom name;
+
+    /* Create CONNECTOR_ID property */
+    name = MakeAtom("CONNECTOR_ID", 12, TRUE);
+    if (name != BAD_RESOURCE) {
+        INT32 value = mode_output->connector_id;
+
+        err = RRConfigureOutputProperty(output->randr_output, name,
+                                        FALSE, FALSE, TRUE, 1, &value);
+        if (err != Success) {
+            xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
+                       "RRConfigureOutputProperty error, %d\n", err);
+        }
+
+        err = RRChangeOutputProperty(output->randr_output, name,
+                                     XA_INTEGER, 32, PropModeReplace, 1,
+                                     &value, FALSE, FALSE);
+        if (err != Success) {
+            xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
+                       "RRChangeOutputProperty error, %d\n", err);
+        }
+    }
 
     drmmode_output->props = calloc(mode_output->count_props + 1, sizeof(drmmode_prop_rec));
     if (!drmmode_output->props)
@@ -1701 +1682 @@
     /* Userspace-only property for TearFree */
     tearfree_prop = calloc(1, sizeof(*tearfree_prop));
     tearfree_prop->flags = DRM_MODE_PROP_ENUM;
-    strncpy(tearfree_prop->name, "TearFree", 8);
+    strcpy(tearfree_prop->name, "TearFree");
     tearfree_prop->count_enums = 3;
     tearfree_prop->enums = calloc(tearfree_prop->count_enums,
                                   sizeof(*tearfree_prop->enums));
-    strncpy(tearfree_prop->enums[0].name, "off", 3);
-    strncpy(tearfree_prop->enums[1].name, "on", 2);
+    strcpy(tearfree_prop->enums[0].name, "off");
+    strcpy(tearfree_prop->enums[1].name, "on");
     tearfree_prop->enums[1].value = 1;
-    strncpy(tearfree_prop->enums[2].name, "auto", 4);
+    strcpy(tearfree_prop->enums[2].name, "auto");
     tearfree_prop->enums[2].value = 2;
     drmmode_output->props[j].mode_prop = tearfree_prop;
     drmmode_output->props[j].value = info->tear_free;
@@ -1776 +1757 @@
     }
 }
 
+static void
+drmmode_output_set_tear_free(RADEONEntPtr pRADEONEnt,
+                             drmmode_output_private_ptr drmmode_output,
+                             xf86CrtcPtr crtc, int tear_free)
+{
+        if (drmmode_output->tear_free == tear_free)
+                return;
+
+        drmmode_output->tear_free = tear_free;
+
+        if (crtc) {
+                drmmode_set_mode_major(crtc, &crtc->mode, crtc->rotation,
+                                       crtc->x, crtc->y);
+        }
+}
+
 static Bool
 drmmode_output_set_property(xf86OutputPtr output, Atom property,
                 RRPropertyValuePtr value)
@@ -1816 +1813 @@
             for (j = 0; j < p->mode_prop->count_enums; j++) {
                 if (!strcmp(p->mode_prop->enums[j].name, name)) {
                     if (i == (drmmode_output->num_props - 1)) {
-                        if (drmmode_output->tear_free != j) {
-                            xf86CrtcPtr crtc = output->crtc;
-
-                            drmmode_output->tear_free = j;
-                            if (crtc) {
-                                drmmode_set_mode_major(crtc, &crtc->mode,
-                                                       crtc->rotation,
-                                                       crtc->x, crtc->y);
-                            }
-                        }
+                        drmmode_output_set_tear_free(pRADEONEnt, drmmode_output,
+                                                     output->crtc, j);
                     } else {
                         drmModeConnectorSetProperty(pRADEONEnt->fd,
                                                     drmmode_output->output_id,
@@ -1853 +1842 @@
     .create_resources = drmmode_output_create_resources,
     .set_property = drmmode_output_set_property,
     .get_property = drmmode_output_get_property,
-#if 0
-
-    .save = drmmode_crt_save,
-    .restore = drmmode_crt_restore,
-    .mode_fixup = drmmode_crt_mode_fixup,
-    .prepare = drmmode_output_prepare,
-    .mode_set = drmmode_crt_mode_set,
-    .commit = drmmode_output_commit,
-#endif
     .detect = drmmode_output_detect,
     .mode_valid = drmmode_output_mode_valid,
 
@@ -2005 +1985 @@
         drmModeEncoderPtr *kencoders = NULL;
         drmmode_output_private_ptr drmmode_output;
         drmModePropertyBlobPtr path_blob = NULL;
+#if XF86_CRTC_VERSION >= 8
+        Bool nonDesktop = FALSE;
+#endif
         char name[32];
         int i;
         const char *s;
@@ -2015 +1998 @@
 
         path_blob = koutput_get_prop_blob(pRADEONEnt->fd, koutput, "PATH");
 
+#if XF86_CRTC_VERSION >= 8
+        i = koutput_get_prop_idx(pRADEONEnt->fd, koutput, DRM_MODE_PROP_RANGE,
+                                 "non-desktop");
+        if (i >= 0)
+                nonDesktop = koutput->prop_values[i] != 0;
+#endif
+
         kencoders = calloc(sizeof(drmModeEncoderPtr), koutput->count_encoders);
         if (!kencoders) {
                 goto out_free_encoders;
@@ -2044 +2034 @@
                         drmmode_output = output->driver_private;
                         drmmode_output->output_id = mode_res->connectors[num];
                         drmmode_output->mode_output = koutput;
+#if XF86_CRTC_VERSION >= 8
+                        output->non_desktop = nonDesktop;
+#endif
                         for (i = 0; i < koutput->count_encoders; i++)
                                 drmModeFreeEncoder(kencoders[i]);
                         free(kencoders);
@@ -2085 +2078 @@
         output->interlaceAllowed = TRUE;
         output->doubleScanAllowed = TRUE;
         output->driver_private = drmmode_output;
+#if XF86_CRTC_VERSION >= 8
+        output->non_desktop = nonDesktop;
+#endif
         
         output->possible_crtcs = 0xffffffff;
         for (i = 0; i < koutput->count_encoders; i++) {
@@ -2266 +2262 @@
 {
         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
         RADEONInfoPtr info = RADEONPTR(scrn);
-        struct radeon_bo *old_front = NULL;
+        struct radeon_buffer *old_front = NULL;
         ScreenPtr   screen = xf86ScrnToScreen(scrn);
         int         i, pitch, old_width, old_height, old_pitch;
-        int aligned_height;
-        uint32_t screen_size;
+        int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP;
         int cpp = info->pixel_bytes;
-        struct radeon_bo *front_bo;
-        struct radeon_surface surface;
-        struct radeon_surface *psurface;
-        uint32_t tiling_flags = 0, base_align;
+        uint32_t tiling_flags;
         PixmapPtr ppix = screen->GetScreenPixmap(screen);
         void *fb_shadow;
 
         if (scrn->virtualX == width && scrn->virtualY == height)
                 return TRUE;
 
-        front_bo = info->front_bo;
-        radeon_cs_flush_indirect(scrn);
-
-        if (front_bo)
-                radeon_bo_wait(front_bo);
-
-        if (info->allowColorTiling && !info->shadow_primary) {
-                if (info->ChipFamily >= CHIP_FAMILY_R600) {
-                        if (info->allowColorTiling2D) {
-                                tiling_flags |= RADEON_TILING_MACRO;
-                        } else {
-                                tiling_flags |= RADEON_TILING_MICRO;
-                        }
-                } else
-                        tiling_flags |= RADEON_TILING_MACRO;
+        if (width > xf86_config->maxWidth || height > xf86_config->maxHeight) {
+                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+                           "Xorg tried resizing screen to %dx%d, but maximum "
+                           "supported is %dx%d\n", width, height,
+                           xf86_config->maxWidth, xf86_config->maxHeight);
+                return FALSE;
         }
 
-        pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp;
-        aligned_height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags));
-        screen_size = RADEON_ALIGN(pitch * aligned_height, RADEON_GPU_PAGE_SIZE);
-        base_align = 4096;
-        if (info->ChipFamily >= CHIP_FAMILY_R600) {
-                memset(&surface, 0, sizeof(struct radeon_surface));
-                surface.npix_x = width;
-                surface.npix_y = height;
-                surface.npix_z = 1;
-                surface.blk_w = 1;
-                surface.blk_h = 1;
-                surface.blk_d = 1;
-                surface.array_size = 1;
-                surface.last_level = 0;
-                surface.bpe = cpp;
-                surface.nsamples = 1;
-                surface.flags = RADEON_SURF_SCANOUT;
-                /* we are requiring a recent enough libdrm version */
-                surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-                surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-                surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-                if (tiling_flags & RADEON_TILING_MICRO) {
-                        surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-                }
-                if (tiling_flags & RADEON_TILING_MACRO) {
-                        surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-                }
-                if (radeon_surface_best(info->surf_man, &surface)) {
-                        return FALSE;
-                }
-                if (radeon_surface_init(info->surf_man, &surface)) {
-                        return FALSE;
-                }
-                screen_size = surface.bo_size;
-                base_align = surface.bo_alignment;
-                pitch = surface.level[0].pitch_bytes;
-                tiling_flags = 0;
-                switch (surface.level[0].mode) {
-                case RADEON_SURF_MODE_2D:
-                        tiling_flags |= RADEON_TILING_MACRO;
-                        tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
-                        tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
-                        tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
-                        if (surface.tile_split)
-                                tiling_flags |= eg_tile_split(surface.tile_split)
-                                                << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
-                        break;
-                case RADEON_SURF_MODE_1D:
-                        tiling_flags |= RADEON_TILING_MICRO;
-                        break;
-                default:
-                        break;
-                }
-                info->front_surface = surface;
+        if (info->allowColorTiling && !info->shadow_primary) {
+                if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D)
+                        usage |= RADEON_CREATE_PIXMAP_TILING_MACRO;
+                else
+                        usage |= RADEON_CREATE_PIXMAP_TILING_MICRO;
         }
 
-        xf86DrvMsg(scrn->scrnIndex, X_INFO,
-                   "Allocate new frame buffer %dx%d stride %d\n",
-                   width, height, pitch / cpp);
+        xf86DrvMsg(scrn->scrnIndex, X_INFO, "Allocate new frame buffer %dx%d\n",
+                   width, height);
 
         old_width = scrn->virtualX;
         old_height = scrn->virtualY;
         old_pitch = scrn->displayWidth;
-        old_front = info->front_bo;
+        old_front = info->front_buffer;
 
         scrn->virtualX = width;
         scrn->virtualY = height;
-        scrn->displayWidth = pitch / cpp;
 
-        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align,
-                                        info->shadow_primary ?
-                                        RADEON_GEM_DOMAIN_GTT :
-                                        RADEON_GEM_DOMAIN_VRAM,
-                                        tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0);
-        if (!info->front_bo)
+        info->front_buffer = radeon_alloc_pixmap_bo(scrn, scrn->virtualX,
+                                                    scrn->virtualY, scrn->depth,
+                                                    usage, scrn->bitsPerPixel,
+                                                    &pitch,
+                                                    &info->front_surface,
+                                                    &tiling_flags);
+        if (!info->front_buffer)
                 goto fail;
 
+        scrn->displayWidth = pitch / cpp;
+
+        if (!info->use_glamor) {
 #if X_BYTE_ORDER == X_BIG_ENDIAN
-        switch (cpp) {
-        case 4:
-            tiling_flags |= RADEON_TILING_SWAP_32BIT;
-            break;
-        case 2:
-            tiling_flags |= RADEON_TILING_SWAP_16BIT;
-            break;
-        }
-        if (info->ChipFamily < CHIP_FAMILY_R600 &&
-            info->r600_shadow_fb && tiling_flags)
-            tiling_flags |= RADEON_TILING_SURFACE;
+                switch (cpp) {
+                case 4:
+                        tiling_flags |= RADEON_TILING_SWAP_32BIT;
+                        break;
+                case 2:
+                        tiling_flags |= RADEON_TILING_SWAP_16BIT;
+                        break;
+                }
+                if (info->ChipFamily < CHIP_FAMILY_R600 &&
+                    info->r600_shadow_fb && tiling_flags)
+                        tiling_flags |= RADEON_TILING_SURFACE;
 #endif
-        if (tiling_flags)
-            radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
+                if (tiling_flags)
+                        radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
+        }
 
         if (!info->r600_shadow_fb) {
-                psurface = radeon_get_pixmap_surface(ppix);
-                *psurface = info->front_surface;
+                if (info->surf_man && !info->use_glamor)
+                        *radeon_get_pixmap_surface(ppix) = info->front_surface;
                 screen->ModifyPixmapHeader(ppix,
                                            width, height, -1, -1, pitch, NULL);
         } else {
-                if (radeon_bo_map(info->front_bo, 1))
+                if (radeon_bo_map(info->front_buffer->bo.radeon, 1))
                         goto fail;
-                fb_shadow = calloc(1, screen_size);
-                if (fb_shadow == NULL)
+                fb_shadow = calloc(1, pitch * scrn->virtualY);
+                if (!fb_shadow)
                         goto fail;
                 free(info->fb_shadow);
                 info->fb_shadow = fb_shadow;
@@ -2416 +2351 @@
                 radeon_glamor_create_screen_resources(scrn->pScreen);
 
         if (!info->r600_shadow_fb) {
-                if (!radeon_set_pixmap_bo(ppix, info->front_bo))
+                if (!radeon_set_pixmap_bo(ppix, info->front_buffer))
                         goto fail;
         }
 
         radeon_pixmap_clear(ppix);
-        radeon_cs_flush_indirect(scrn);
-        radeon_bo_wait(info->front_bo);
+        radeon_finish(scrn, info->front_buffer);
 
         for (i = 0; i < xf86_config->num_crtc; i++) {
                 xf86CrtcPtr crtc = xf86_config->crtc[i];
@@ -2434 +2368 @@
                                        crtc->rotation, crtc->x, crtc->y);
         }
 
-        if (old_front)
-                radeon_bo_unref(old_front);
+        radeon_buffer_unref(&old_front);
 
-        radeon_kms_update_vram_limit(scrn, screen_size);
+        radeon_kms_update_vram_limit(scrn, pitch * scrn->virtualY);
         return TRUE;
 
  fail:
-        if (info->front_bo)
-                radeon_bo_unref(info->front_bo);
-        info->front_bo = old_front;
+        radeon_buffer_unref(&info->front_buffer);
+        info->front_buffer = old_front;
         scrn->virtualX = old_width;
         scrn->virtualY = old_height;
         scrn->displayWidth = old_pitch;
@@ -2451 +2383 @@
         return FALSE;
 }
 
+static void
+drmmode_validate_leases(ScrnInfoPtr scrn)
+{
+#ifdef XF86_LEASE_VERSION
+        ScreenPtr screen = scrn->pScreen;
+        rrScrPrivPtr scr_priv = rrGetScrPriv(screen);
+        RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
+        drmModeLesseeListPtr lessees;
+        RRLeasePtr lease, next;
+        int l;
+
+        /* We can't talk to the kernel about leases when VT switched */
+        if (!scrn->vtSema)
+                return;
+
+        lessees = drmModeListLessees(pRADEONEnt->fd);
+        if (!lessees)
+                return;
+
+        xorg_list_for_each_entry_safe(lease, next, &scr_priv->leases, list) {
+                drmmode_lease_private_ptr lease_private = lease->devPrivate;
+
+                for (l = 0; l < lessees->count; l++) {
+                        if (lessees->lessees[l] == lease_private->lessee_id)
+                                break;
+                }
+
+                /* check to see if the lease has gone away */
+                if (l == lessees->count) {
+                        free(lease_private);
+                        lease->devPrivate = NULL;
+                        xf86CrtcLeaseTerminated(lease);
+                }
+        }
+
+        free(lessees);
+#endif
+}
+
+#ifdef XF86_LEASE_VERSION
+
+static int
+drmmode_create_lease(RRLeasePtr lease, int *fd)
+{
+        ScreenPtr screen = lease->screen;
+        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+        RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
+        drmmode_lease_private_ptr lease_private;
+        int noutput = lease->numOutputs;
+        int ncrtc = lease->numCrtcs;
+        uint32_t *objects;
+        size_t nobjects;
+        int lease_fd;
+        int c, o;
+        int i;
+
+        nobjects = ncrtc + noutput;
+        if (nobjects == 0 || nobjects > (SIZE_MAX / 4) ||
+            ncrtc > (SIZE_MAX - noutput))
+                return BadValue;
+
+        lease_private = calloc(1, sizeof (drmmode_lease_private_rec));
+        if (!lease_private)
+                return BadAlloc;
+
+        objects = malloc(nobjects * 4);
+        if (!objects) {
+                free(lease_private);
+                return BadAlloc;
+        }
+
+        i = 0;
+
+        /* Add CRTC ids */
+        for (c = 0; c < ncrtc; c++) {
+                xf86CrtcPtr crtc = lease->crtcs[c]->devPrivate;
+                drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+                objects[i++] = drmmode_crtc->mode_crtc->crtc_id;
+        }
+
+        /* Add connector ids */
+        for (o = 0; o < noutput; o++) {
+                xf86OutputPtr   output = lease->outputs[o]->devPrivate;
+                drmmode_output_private_ptr drmmode_output = output->driver_private;
+
+                objects[i++] = drmmode_output->mode_output->connector_id;
+        }
+
+        /* call kernel to create lease */
+        assert (i == nobjects);
+
+        lease_fd = drmModeCreateLease(pRADEONEnt->fd, objects, nobjects, 0,
+                                      &lease_private->lessee_id);
+
+        free(objects);
+
+        if (lease_fd < 0) {
+                free(lease_private);
+                return BadMatch;
+        }
+
+        lease->devPrivate = lease_private;
+
+        xf86CrtcLeaseStarted(lease);
+
+        *fd = lease_fd;
+        return Success;
+}
+
+static void
+drmmode_terminate_lease(RRLeasePtr lease)
+{
+        drmmode_lease_private_ptr lease_private = lease->devPrivate;
+        ScreenPtr screen = lease->screen;
+        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+        RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
+
+        if (drmModeRevokeLease(pRADEONEnt->fd, lease_private->lessee_id) == 0) {
+                free(lease_private);
+                lease->devPrivate = NULL;
+                xf86CrtcLeaseTerminated(lease);
+        }
+}
+
+#endif // XF86_LEASE_VERSION
+
 static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = {
-        drmmode_xf86crtc_resize
+        .resize = drmmode_xf86crtc_resize,
+#ifdef XF86_LEASE_VERSION
+        .create_lease = drmmode_create_lease,
+        .terminate_lease = drmmode_terminate_lease
+#endif
 };
 
 static void
@@ -2461 +2524 @@
         drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
         RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
         drmmode_flipdata_ptr flipdata = event_data;
+        int crtc_id = drmmode_get_crtc_id(crtc);
+        struct drmmode_fb **fb = &flipdata->fb[crtc_id];
+
+        if (drmmode_crtc->flip_pending == *fb) {
+                drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,
+                                     NULL);
+        }
+        drmmode_fb_reference(pRADEONEnt->fd, fb, NULL);
 
         if (--flipdata->flip_count == 0) {
                 if (!flipdata->fe_crtc)
                         flipdata->fe_crtc = crtc;
                 flipdata->abort(flipdata->fe_crtc, flipdata->event_data);
-                drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);
                 free(flipdata);
         }
-
-        drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,
-                             NULL);
 }
 
 static void
@@ -2480 +2547 @@
         drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
         RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
         drmmode_flipdata_ptr flipdata = event_data;
+        int crtc_id = drmmode_get_crtc_id(crtc);
+        struct drmmode_fb **fb = &flipdata->fb[crtc_id];
 
         /* Is this the event whose info shall be delivered to higher level? */
         if (crtc == flipdata->fe_crtc) {
@@ -2488 +2557 @@
                 flipdata->fe_usec = usec;
         }
 
-        drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb,
-                             flipdata->fb);
-        if (drmmode_crtc->tear_free ||
-            drmmode_crtc->flip_pending == flipdata->fb) {
+        if (drmmode_crtc->flip_pending == *fb) {
                 drmmode_fb_reference(pRADEONEnt->fd,
                                      &drmmode_crtc->flip_pending, NULL);
         }
+        drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, *fb);
+        drmmode_fb_reference(pRADEONEnt->fd, fb, NULL);
 
         if (--flipdata->flip_count == 0) {
                 /* Deliver MSC & UST from reference/current CRTC to flip event
@@ -2506 +2574 @@
                 else
                         flipdata->handler(crtc, frame, usec, flipdata->event_data);
 
-                drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);
                 free(flipdata);
         }
 }
@@ -2520 +2587 @@
 drm_wakeup_handler(pointer data, int err, pointer p)
 #endif
 {
-        ScrnInfoPtr scrn = data;
-        RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
-        RADEONInfoPtr info = RADEONPTR(scrn);
+        drmmode_ptr drmmode = data;
+        RADEONEntPtr pRADEONEnt = RADEONEntPriv(drmmode->scrn);
         
 #if !HAVE_NOTIFY_FD
         fd_set *read_mask = p;
@@ -2530 +2596 @@
         if (err >= 0 && FD_ISSET(pRADEONEnt->fd, read_mask))
 #endif
         {
-                drmHandleEvent(pRADEONEnt->fd, &info->drmmode.event_context);
+                radeon_drm_handle_event(pRADEONEnt->fd, &drmmode->event_context);
         }
 }
 
@@ -2663 +2729 @@
 
         xf86InitialConfiguration(pScrn, TRUE);
 
-        drmmode->event_context.version = 2;
-        drmmode->event_context.vblank_handler = radeon_drm_queue_handler;
-        drmmode->event_context.page_flip_handler = radeon_drm_queue_handler;
-
         pRADEONEnt->has_page_flip_target = drmmode_probe_page_flip_target(pRADEONEnt);
 
         drmModeFreeResources(mode_res);
@@ -2684 +2746 @@
         info->drmmode_inited = TRUE;
         if (pRADEONEnt->fd_wakeup_registered != serverGeneration) {
 #if HAVE_NOTIFY_FD
-                SetNotifyFd(pRADEONEnt->fd, drm_notify_fd, X_NOTIFY_READ, pScrn);
+                SetNotifyFd(pRADEONEnt->fd, drm_notify_fd, X_NOTIFY_READ,
+                            &info->drmmode);
 #else
                 AddGeneralSocket(pRADEONEnt->fd);
                 RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA,
-                                drm_wakeup_handler, pScrn);
+                                               drm_wakeup_handler,
+                                               &info->drmmode);
 #endif
                 pRADEONEnt->fd_wakeup_registered = serverGeneration;
                 pRADEONEnt->fd_wakeup_ref = 1;
@@ -2853 +2917 @@
                                Bool set_hw)
 {
         xf86CrtcConfigPtr   config = XF86_CRTC_CONFIG_PTR(pScrn);
-        RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
         unsigned num_desired = 0, num_on = 0;
         int c;
 
@@ -2861 +2924 @@
         if (set_hw) {
                 for (c = 0; c < config->num_crtc; c++) {
                         xf86CrtcPtr crtc = config->crtc[c];
-                        drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
 
                         /* Skip disabled CRTCs */
                         if (crtc->enabled)
                                 continue;
 
-                        drmmode_do_crtc_dpms(crtc, DPMSModeOff);
-                        drmModeSetCrtc(pRADEONEnt->fd,
-                                       drmmode_crtc->mode_crtc->crtc_id,
-                                       0, 0, 0, NULL, 0, NULL);
-                        drmmode_fb_reference(pRADEONEnt->fd,
-                                             &drmmode_crtc->fb, NULL);
+                        drmmode_crtc_dpms(crtc, DPMSModeOff);
                 }
         }
 
@@ -2928 +2985 @@
                         } else {
                                 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
                                            "Failed to set mode on CRTC %d\n", c);
+                                RRCrtcSet(crtc->randr_crtc, NULL, crtc->x, crtc->y,
+                                          crtc->rotation, 0, NULL);
                         }
                 } else {
                         crtc->mode = crtc->desiredMode;
@@ -2944 +3003 @@
                 return FALSE;
         }
 
+        /* Validate leases on VT re-entry */
+        drmmode_validate_leases(pScrn);
+
         return TRUE;
 }
 
 Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn)
 {
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+    int i;
 
     if (xf86_config->num_crtc) {
         xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
@@ -2958 +3021 @@
             return FALSE;
 
         /* All radeons support 10 bit CLUTs. They get bypassed at depth 30. */
-        if (pScrn->depth != 30 &&
-            !xf86HandleColormaps(pScreen, 256, 10,
-                                 NULL, NULL,
-                                 CMAP_PALETTED_TRUECOLOR
-#if 0 /* This option messes up text mode! (eich@suse.de) */
-                                 | CMAP_LOAD_EVEN_IF_OFFSCREEN
-#endif
-                                 | CMAP_RELOAD_ON_MODE_SWITCH))
-            return FALSE;
+        if (pScrn->depth != 30) {
+            if (!xf86HandleColormaps(pScreen, 256, 10, NULL, NULL,
+                                     CMAP_PALETTED_TRUECOLOR
+                                     | CMAP_RELOAD_ON_MODE_SWITCH))
+                return FALSE;
+
+            for (i = 0; i < xf86_config->num_crtc; i++) {
+                xf86CrtcPtr crtc = xf86_config->crtc[i];
+
+                drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red,
+                                          crtc->gamma_green,
+                                          crtc->gamma_blue,
+                                          crtc->gamma_size);
+            }
+        }
     }
+
     return TRUE;
 }
 
@@ -3103 +3173 @@
                         changed = TRUE;
         }
 
+        /* Check to see if a lessee has disappeared */
+        drmmode_validate_leases(scrn);
+
         if (changed && dixPrivateKeyRegistered(rrPrivKey)) {
 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0)
                 RRSetChanged(xf86ScrnToScreen(scrn));
@@ -3203 +3276 @@
         xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
         xf86CrtcPtr crtc = NULL;
         drmmode_crtc_private_ptr drmmode_crtc = config->crtc[0]->driver_private;
-        int i;
         uint32_t flip_flags = flip_sync == FLIP_ASYNC ? DRM_MODE_PAGE_FLIP_ASYNC : 0;
         drmmode_flipdata_ptr flipdata;
+        Bool handle_deferred = FALSE;
         uintptr_t drm_queue_seq = 0;
+        struct drmmode_fb *fb;
+        int i = 0;
 
-        flipdata = calloc(1, sizeof(drmmode_flipdata_rec));
+        flipdata = calloc(1, sizeof(*flipdata) + config->num_crtc *
+                          sizeof(flipdata->fb[0]));
         if (!flipdata) {
              xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                         "flip queue: data alloc failed.\n");
              goto error;
         }
 
-        drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb,
-                             radeon_pixmap_get_fb(new_front));
-        if (!flipdata->fb) {
+        fb = radeon_pixmap_get_fb(new_front);
+        if (!fb) {
                 ErrorF("Failed to get FB for flip\n");
                 goto error;
         }
@@ -3238 +3313 @@
         flipdata->fe_crtc = ref_crtc;
 
         for (i = 0; i < config->num_crtc; i++) {
-                struct drmmode_fb *fb = flipdata->fb;
-
                 crtc = config->crtc[i];
                 drmmode_crtc = crtc->driver_private;
 
@@ -3275 +3348 @@
                                 goto next;
                         }
 
-                        fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap);
-                        if (!fb) {
+                        drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb[i],
+                                             radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap));
+                        if (!flipdata->fb[i]) {
                                 ErrorF("Failed to get FB for TearFree flip\n");
                                 goto error;
                         }
 
                         radeon_scanout_do_update(crtc, scanout_id, new_front,
                                                  extents);
+                        radeon_cs_flush_indirect(crtc->scrn);
 
-                        drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd,
-                                                        drmmode_crtc->scanout_update_pending);
+                        if (drmmode_crtc->scanout_update_pending) {
+                                radeon_drm_wait_pending_flip(crtc);
+                                handle_deferred = TRUE;
+                                radeon_drm_abort_entry(drmmode_crtc->scanout_update_pending);
+                                drmmode_crtc->scanout_update_pending = 0;
+                        }
+                } else {
+                        drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb[i], fb);
                 }
 
                 if (crtc == ref_crtc) {
                         if (drmmode_page_flip_target_absolute(pRADEONEnt,
                                                               drmmode_crtc,
-                                                              fb->handle,
+                                                              flipdata->fb[i]->handle,
                                                               flip_flags,
                                                               drm_queue_seq,
                                                               target_msc) != 0)
@@ -3299 +3380 @@
                 } else {
                         if (drmmode_page_flip_target_relative(pRADEONEnt,
                                                               drmmode_crtc,
-                                                              fb->handle,
+                                                              flipdata->fb[i]->handle,
                                                               flip_flags,
                                                               drm_queue_seq, 0) != 0)
                                 goto flip_error;
@@ -3311 +3392 @@
                 }
 
         next:
-                drmmode_fb_reference(pRADEONEnt->fd,
-                                     &drmmode_crtc->flip_pending, fb);
+                drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,
+                                     flipdata->fb[i]);
                 drm_queue_seq = 0;
         }
 
+        if (handle_deferred)
+                radeon_drm_queue_handle_deferred(ref_crtc);
         if (flipdata->flip_count > 0)
                 return TRUE;
 
@@ -3330 +3413 @@
                 drmmode_flip_abort(crtc, flipdata);
         else {
                 abort(NULL, data);
-                drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);
                 free(flipdata);
         }
 
         xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Page flip failed: %s\n",
                    strerror(errno));
+        if (handle_deferred)
+                radeon_drm_queue_handle_deferred(ref_crtc);
         return FALSE;
 }

src/drmmode_display.h

@@ -56 +56 @@
 } drmmode_rec, *drmmode_ptr;
 
 typedef struct {
-  struct drmmode_fb *fb;
   void *event_data;
   int flip_count;
   unsigned int fe_frame;
@@ -64 +63 @@
   xf86CrtcPtr fe_crtc;
   radeon_drm_handler_proc handler;
   radeon_drm_abort_proc abort;
+  struct drmmode_fb *fb[0];
 } drmmode_flipdata_rec, *drmmode_flipdata_ptr;
 
 struct drmmode_fb {
@@ -72 +72 @@
 };
 
 struct drmmode_scanout {
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
     PixmapPtr pixmap;
     int width, height;
 };
@@ -88 +88 @@
     Bool ignore_damage;
     RegionRec scanout_last_region;
     unsigned scanout_id;
-    Bool scanout_update_pending;
+    uintptr_t scanout_update_pending;
     Bool tear_free;
 
     PixmapPtr prime_scanout_pixmap;
@@ -103 +103 @@
      * modeset)
      */
     Bool need_modeset;
+    /* For keeping track of nested calls to drm_wait_pending_flip /
+     * drm_queue_handle_deferred
+     */
+    int wait_flip_nesting_level;
     /* A flip to this FB is pending for this CRTC */
     struct drmmode_fb *flip_pending;
     /* The FB currently being scanned out by this CRTC, if any */
     struct drmmode_fb *fb;
-
-#ifdef HAVE_PRESENT_H
-    /* Deferred processing of Present vblank event */
-    uint64_t present_vblank_event_id;
-    uint64_t present_vblank_usec;
-    unsigned present_vblank_msc;
-    Bool present_flip_expected;
-#endif
 } drmmode_crtc_private_rec, *drmmode_crtc_private_ptr;
 
 typedef struct {
@@ -139 +135 @@
     int tear_free;
 } drmmode_output_private_rec, *drmmode_output_private_ptr;
 
+typedef struct {
+    uint32_t lessee_id;
+} drmmode_lease_private_rec, *drmmode_lease_private_ptr;
+
 
 enum drmmode_flip_sync {
     FLIP_VSYNC,

xf86-video-ati-18.0.1

@@ -71 +71 @@
     if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
         RADEON_FALLBACK(("invalid planemask\n"));
 
-    dst.bo = radeon_get_pixmap_bo(pPix);
+    dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
     dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
     dst.surface = radeon_get_pixmap_surface(pPix);
 
@@ -466 +466 @@
 
     accel_state->same_surface = FALSE;
 
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
     src_obj.surface = radeon_get_pixmap_surface(pSrc);
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
-    if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
+    if (src_obj.bo == dst_obj.bo)
         accel_state->same_surface = TRUE;
 
     src_obj.width = pSrc->drawable.width;
@@ -511 +511 @@
         accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
                                                    RADEON_GEM_DOMAIN_VRAM,
                                                    0);
-        if (accel_state->copy_area_bo == NULL)
+        if (!accel_state->copy_area_bo)
             RADEON_FALLBACK(("temp copy surface alloc failed\n"));
 
         radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
@@ -1301 +1301 @@
         return FALSE;
 
     if (pSrc) {
-        src_obj.bo = radeon_get_pixmap_bo(pSrc);
+        src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
         src_obj.surface = radeon_get_pixmap_surface(pSrc);
         src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
         src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
@@ -1311 +1311 @@
         src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
     }
 
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1325 +1325 @@
 
     if (pMaskPicture) {
         if (pMask) {
-            mask_obj.bo = radeon_get_pixmap_bo(pMask);
+            mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon;
             mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
             mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
             mask_obj.surface = radeon_get_pixmap_surface(pMask);
@@ -1673 +1673 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pDst);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
     /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
-    copy_dst = driver_priv->bo;
+    copy_dst = driver_priv->bo->bo.radeon;
     copy_pitch = pDst->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
             flush = FALSE;
-            if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+            if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
                 !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
                 goto copy;
         }
@@ -1693 +1693 @@
     base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0);
     size = scratch_pitch * height * (bpp / 8);
     scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
 
@@ -1711 +1711 @@
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = bpp;
     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
 
@@ -1739 +1739 @@
     r = TRUE;
     size = w * bpp / 8;
     dst = copy_dst->ptr;
-    if (copy_dst == driver_priv->bo)
+    if (copy_dst == driver_priv->bo->bo.radeon)
         dst += y * copy_pitch + x * bpp / 8;
     for (i = 0; i < h; i++) {
         memcpy(dst + i * copy_pitch, src, size);
@@ -1789 +1789 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
     /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
-    copy_src = driver_priv->bo;
+    copy_src = driver_priv->bo->bo.radeon;
     copy_pitch = pSrc->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
-            src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+        if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
+            src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
             if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
                 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
                 src_domain = 0;
@@ -1806 +1806 @@
         }
 
         if (!src_domain)
-            radeon_bo_is_busy(driver_priv->bo, &src_domain);
+            radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);
 
         if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
             goto copy;
@@ -1821 +1821 @@
     base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0);
     size = scratch_pitch * height * (bpp / 8);
     scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
     radeon_cs_space_reset_bos(info->cs);
@@ -1841 +1841 @@
     src_obj.height = pSrc->drawable.height;
     src_obj.bpp = bpp;
     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
     src_obj.surface = radeon_get_pixmap_surface(pSrc);
 
@@ -1883 +1883 @@
     }
     r = TRUE;
     w *= bpp / 8;
-    if (copy_src == driver_priv->bo)
+    if (copy_src == driver_priv->bo->bo.radeon)
         size = y * copy_pitch + x * bpp / 8;
     else
         size = 0;
@@ -1927 +1927 @@
 
     accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
                                              RADEON_GEM_DOMAIN_VRAM, 0);
-    if (accel_state->shaders_bo == NULL) {
+    if (!accel_state->shaders_bo) {
         ErrorF("Allocating shader failed\n");
         return FALSE;
     }
@@ -2046 +2046 @@
     ScrnInfoPtr pScrn =  xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info   = RADEONPTR(pScrn);
 
-    if (info->accel_state->exa == NULL) {
+    if (!info->accel_state->exa) {
         xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
         return FALSE;
     }
@@ -2065 +2065 @@
     info->accel_state->exa->MarkSync = EVERGREENMarkSync;
     info->accel_state->exa->WaitMarker = EVERGREENSync;
 
-    info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
     info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
     info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
     info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;

src/evergreen_state.h

@@ -345 +345 @@
 
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
                                     int depth, int usage_hint, int bitsPerPixel,
                                     int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
-extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p);
 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);

src/evergreen_textured_videofuncs.c

@@ -140 +140 @@
     CLEAR (vs_const_conf);
     CLEAR (ps_const_conf);
 
-    dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+    dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
     dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
 

xf86-video-ati-18.0.1

@@ -150 +150 @@
     if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
         RADEON_FALLBACK(("invalid planemask\n"));
 
-    dst.bo = radeon_get_pixmap_bo(pPix);
+    dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
     dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
     dst.surface = radeon_get_pixmap_surface(pPix);
 
@@ -534 +534 @@
 
     accel_state->same_surface = FALSE;
 
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
     src_obj.surface = radeon_get_pixmap_surface(pSrc);
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
-    if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
+    if (src_obj.bo == dst_obj.bo)
         accel_state->same_surface = TRUE;
 
     src_obj.width = pSrc->drawable.width;
@@ -575 +575 @@
         accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align,
                                                    RADEON_GEM_DOMAIN_VRAM,
                                                    0);
-        if (accel_state->copy_area_bo == NULL)
+        if (!accel_state->copy_area_bo)
             RADEON_FALLBACK(("temp copy surface alloc failed\n"));
         
         radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
@@ -1344 +1344 @@
         return FALSE;
 
     if (pSrc) {
-        src_obj.bo = radeon_get_pixmap_bo(pSrc);
+        src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
         src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
         src_obj.surface = radeon_get_pixmap_surface(pSrc);
         src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
@@ -1354 +1354 @@
         src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
     }
 
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1368 +1368 @@
 
     if (pMaskPicture) {
         if (pMask) {
-            mask_obj.bo = radeon_get_pixmap_bo(pMask);
+            mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon;
             mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
             mask_obj.surface = radeon_get_pixmap_surface(pMask);
             mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
@@ -1700 +1700 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pDst);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
     /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
-    copy_dst = driver_priv->bo;
+    copy_dst = driver_priv->bo->bo.radeon;
     copy_pitch = pDst->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
             flush = FALSE;
-            if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+            if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
                 !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
                 goto copy;
         }
@@ -1723 +1723 @@
     base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0);
     size = scratch_pitch * height * (bpp / 8);
     scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
 
@@ -1741 +1741 @@
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = bpp;
     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
     dst_obj.surface = radeon_get_pixmap_surface(pDst);
 
@@ -1769 +1769 @@
     r = TRUE;
     size = w * bpp / 8;
     dst = copy_dst->ptr;
-    if (copy_dst == driver_priv->bo)
+    if (copy_dst == driver_priv->bo->bo.radeon)
         dst += y * copy_pitch + x * bpp / 8;
     for (i = 0; i < h; i++) {
         memcpy(dst + i * copy_pitch, src, size);
@@ -1819 +1819 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
     /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
-    copy_src = driver_priv->bo;
+    copy_src = driver_priv->bo->bo.radeon;
     copy_pitch = pSrc->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
-            src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+        if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
+            src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
             if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
                 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
                 src_domain = 0;
@@ -1836 +1836 @@
         }
 
         if (!src_domain)
-            radeon_bo_is_busy(driver_priv->bo, &src_domain);
+            radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);
 
         if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
             goto copy;
@@ -1847 +1847 @@
     base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0);
     size = scratch_pitch * height * (bpp / 8);
     scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
     radeon_cs_space_reset_bos(info->cs);
@@ -1867 +1867 @@
     src_obj.height = pSrc->drawable.height;
     src_obj.bpp = bpp;
     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
     src_obj.surface = radeon_get_pixmap_surface(pSrc);
 
@@ -1909 +1909 @@
     }
     r = TRUE;
     w *= bpp / 8;
-    if (copy_src == driver_priv->bo)
+    if (copy_src == driver_priv->bo->bo.radeon)
         size = y * copy_pitch + x * bpp / 8;
     else
         size = 0;
@@ -1960 +1960 @@
 
     accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
                                              RADEON_GEM_DOMAIN_VRAM, 0);
-    if (accel_state->shaders_bo == NULL) {
+    if (!accel_state->shaders_bo) {
         ErrorF("Allocating shader failed\n");
         return FALSE;
     }
@@ -2025 +2025 @@
     ScrnInfoPtr pScrn =  xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info   = RADEONPTR(pScrn);
 
-    if (info->accel_state->exa == NULL) {
+    if (!info->accel_state->exa) {
         xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
         return FALSE;
     }
@@ -2044 +2044 @@
     info->accel_state->exa->MarkSync = R600MarkSync;
     info->accel_state->exa->WaitMarker = R600Sync;
 
-    info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
     info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
     info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
     info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;

xf86-video-ati-18.0.1

@@ -316 +316 @@
 
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
                                     int depth, int usage_hint, int bitsPerPixel,
                                     int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
-extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p);
 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);

src/r600_textured_videofuncs.c

@@ -152 +152 @@
     CLEAR (vs_conf);
     CLEAR (ps_conf);
 
-    dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+    dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
     dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
 

src/radeon_bo_helper.c

@@ -28 +28 @@
 #include "radeon_glamor.h"
 #include "radeon_bo_gem.h"
 
+
+#ifdef USE_GLAMOR
+
+static uint32_t
+radeon_get_gbm_format(int depth, int bitsPerPixel)
+{
+    switch (depth) {
+#ifdef GBM_FORMAT_R8
+    case 8:
+        return GBM_FORMAT_R8;
+#endif
+    case 16:
+        return GBM_FORMAT_RGB565;
+    case 32:
+        return GBM_FORMAT_ARGB8888;
+    case 30:
+        return GBM_FORMAT_XRGB2101010;
+    case 24:
+        if (bitsPerPixel == 32)
+            return GBM_FORMAT_XRGB8888;
+        /* fall through */
+    default:
+        ErrorF("%s: Unsupported depth/bpp %d/%d\n", __func__, depth,
+               bitsPerPixel);
+        return ~0U;
+    }
+}
+
+#endif /* USE_GLAMOR */
+
+
 static const unsigned MicroBlockTable[5][3][2] = {
     /*linear  tiled   square-tiled */
     {{32, 1}, {8, 4}, {0, 0}}, /*   8 bits per pixel */
@@ -59 +90 @@
     }
 }
 
+static unsigned eg_tile_split_opp(unsigned tile_split)
+{
+    switch (tile_split) {
+        case 0:     tile_split = 64;    break;
+        case 1:     tile_split = 128;   break;
+        case 2:     tile_split = 256;   break;
+        case 3:     tile_split = 512;   break;
+        default:
+        case 4:     tile_split = 1024;  break;
+        case 5:     tile_split = 2048;  break;
+        case 6:     tile_split = 4096;  break;
+    }
+    return tile_split;
+}
+
+Bool
+radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
+                          int width, int height, int cpp, uint32_t tiling_flags,
+                          int usage_hint)
+{
+        memset(surface, 0, sizeof(struct radeon_surface));
+
+        surface->npix_x = width;
+        /* need to align height to 8 for old kernel */
+        surface->npix_y = RADEON_ALIGN(height, 8);
+        surface->npix_z = 1;
+        surface->blk_w = 1;
+        surface->blk_h = 1;
+        surface->blk_d = 1;
+        surface->array_size = 1;
+        surface->last_level = 0;
+        surface->bpe = cpp;
+        surface->nsamples = 1;
+        if (height < 128) {
+            /* disable 2d tiling for small surface to work around
+             * the fact that ddx align height to 8 pixel for old
+             * obscure reason i can't remember
+             */
+            tiling_flags &= ~RADEON_TILING_MACRO;
+        }
+
+        surface->flags = RADEON_SURF_SCANOUT | RADEON_SURF_HAS_TILE_MODE_INDEX |
+            RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+
+        if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
+            surface->flags |= RADEON_SURF_ZBUFFER;
+            surface->flags |= RADEON_SURF_SBUFFER;
+        }
+
+        if ((tiling_flags & RADEON_TILING_MACRO)) {
+            surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+        } else if ((tiling_flags & RADEON_TILING_MICRO)) {
+            surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+        } else
+            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+
+        if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+            surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
+                RADEON_TILING_EG_BANKW_MASK;
+            surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
+                RADEON_TILING_EG_BANKH_MASK;
+            surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
+                                                    RADEON_TILING_EG_TILE_SPLIT_MASK);
+            if (surface->flags & RADEON_SURF_SBUFFER) {
+                surface->stencil_tile_split =
+                    (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
+                    RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
+            }
+            surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
+                RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
+        }
+
+        if (radeon_surface_best(info->surf_man, surface))
+            return FALSE;
+
+        if (radeon_surface_init(info->surf_man, surface))
+            return FALSE;
+
+        return TRUE;
+}
+
 /* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that
  * can hold it.
  */
-struct radeon_bo*
+struct radeon_buffer *
 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
                        int usage_hint, int bitsPerPixel, int *new_pitch,
                        struct radeon_surface *new_surface, uint32_t *new_tiling)
@@ -73 +187 @@
     int cpp = bitsPerPixel / 8;
     uint32_t tiling = 0, flags = 0;
     struct radeon_surface surface;
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
     int domain = RADEON_GEM_DOMAIN_VRAM;
+
+#ifdef USE_GLAMOR
+    if (info->use_glamor &&
+        !(usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
+          info->shadow_primary)) {
+        uint32_t bo_use = GBM_BO_USE_RENDERING;
+        uint32_t gbm_format = radeon_get_gbm_format(depth, bitsPerPixel);
+
+        if (gbm_format == ~0U)
+            return NULL;
+
+        bo = calloc(1, sizeof(struct radeon_buffer));
+        if (!bo)
+            return NULL;
+
+        bo->ref_count = 1;
+
+        if (bitsPerPixel == pScrn->bitsPerPixel)
+            bo_use |= GBM_BO_USE_SCANOUT;
+
+        if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
+             info->shadow_primary) ||
+            (usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED)
+            bo_use |= GBM_BO_USE_LINEAR;
+
+        bo->bo.gbm = gbm_bo_create(info->gbm, width, height, gbm_format, bo_use);
+        if (!bo->bo.gbm) {
+            free(bo);
+            return NULL;
+        }
+
+        bo->flags |= RADEON_BO_FLAGS_GBM;
+
+        if (new_pitch)
+            *new_pitch = gbm_bo_get_stride(bo->bo.gbm);
+
+        return bo;
+    }
+#endif
+
     if (usage_hint) {
         if (info->allowColorTiling) {
             if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO)
@@ -107 +261 @@
     pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp;
     base_align = drmmode_get_base_align(pScrn, cpp, tiling);
     size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
-    memset(&surface, 0, sizeof(struct radeon_surface));
 
-    if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
-                if (width) {
-                        surface.npix_x = width;
-                        /* need to align height to 8 for old kernel */
-                        surface.npix_y = RADEON_ALIGN(height, 8);
-                        surface.npix_z = 1;
-                        surface.blk_w = 1;
-                        surface.blk_h = 1;
-                        surface.blk_d = 1;
-                        surface.array_size = 1;
-                        surface.last_level = 0;
-                        surface.bpe = cpp;
-                        surface.nsamples = 1;
-                        if (height < 128) {
-                                /* disable 2d tiling for small surface to work around
-                                 * the fact that ddx align height to 8 pixel for old
-                                 * obscure reason i can't remember
-                                 */
-                                tiling &= ~RADEON_TILING_MACRO;
-                        }
-                        surface.flags = RADEON_SURF_SCANOUT;
-                        /* we are requiring a recent enough libdrm version */
-                        surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
-                        if ((tiling & RADEON_TILING_MICRO)) {
-                                surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                                surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-                        }
-                        if ((tiling & RADEON_TILING_MACRO)) {
-                                surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                                surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-                        }
-                        if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
-                                surface.flags |= RADEON_SURF_ZBUFFER;
-                                surface.flags |= RADEON_SURF_SBUFFER;
-                        }
-                        if (radeon_surface_best(info->surf_man, &surface)) {
-                                return NULL;
-                        }
-                        if (radeon_surface_init(info->surf_man, &surface)) {
-                                return NULL;
-                        }
-                        size = surface.bo_size;
-                        base_align = surface.bo_alignment;
-                        pitch = surface.level[0].pitch_bytes;
-                        tiling = 0;
-                        switch (surface.level[0].mode) {
-                        case RADEON_SURF_MODE_2D:
-                                tiling |= RADEON_TILING_MACRO;
-                                tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
-                                tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
-                                tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
-                                if (surface.tile_split)
-                                        tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
-                                tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
-                                break;
-                        case RADEON_SURF_MODE_1D:
-                                tiling |= RADEON_TILING_MICRO;
-                                break;
-                        default:
-                                break;
-                        }
-                }
+    if (width && info->surf_man) {
+        if (!radeon_surface_initialize(info, &surface, width, height, cpp,
+                                       tiling, usage_hint))
+            return NULL;
+
+        size = surface.bo_size;
+        base_align = surface.bo_alignment;
+        pitch = surface.level[0].pitch_bytes;
+        tiling = 0;
+        switch (surface.level[0].mode) {
+        case RADEON_SURF_MODE_2D:
+            tiling |= RADEON_TILING_MACRO;
+            tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
+            tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
+            tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
+            if (surface.tile_split)
+                tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+            if (surface.flags & RADEON_SURF_SBUFFER)
+                tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
+            break;
+        case RADEON_SURF_MODE_1D:
+            tiling |= RADEON_TILING_MICRO;
+            break;
+        default:
+            break;
         }
 
+        if (new_surface)
+            *new_surface = surface;
+    }
+
     if (tiling)
         flags |= RADEON_GEM_NO_CPU_ACCESS;
 
-    bo = radeon_bo_open(info->bufmgr, 0, size, base_align,
-                        domain, flags);
+    bo = calloc(1, sizeof(struct radeon_buffer));
+    if (!bo)
+        return NULL;
+
+    bo->ref_count = 1;
+    bo->bo.radeon = radeon_bo_open(info->bufmgr, 0, size, base_align,
+                                   domain, flags);
 
-    if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0)
+    if (bo && tiling && radeon_bo_set_tiling(bo->bo.radeon, tiling, pitch) == 0)
         *new_tiling = tiling;
 
-    *new_surface = surface;
     *new_pitch = pitch;
     return bo;
 }
 
+
+/* Flush and wait for the BO to become idle */
+void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo)
+{
+    RADEONInfoPtr info = RADEONPTR(scrn);
+
+    if (info->use_glamor) {
+        radeon_glamor_finish(scrn);
+        return;
+    }
+
+    radeon_cs_flush_indirect(scrn);
+    radeon_bo_wait(bo->bo.radeon);
+}
+
+
 /* Clear the pixmap contents to black */
 void
 radeon_pixmap_clear(PixmapPtr pixmap)
@@ -213 +352 @@
 /* Get GEM handle for the pixmap */
 Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
 {
-    struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);
+    struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap);
 #ifdef USE_GLAMOR
     ScreenPtr screen = pixmap->drawable.pScreen;
     ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
@@ -221 +360 @@
     RADEONInfoPtr info = RADEONPTR(scrn);
 #endif
 
-    if (bo) {
-        *handle = bo->handle;
+    if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM)) {
+        *handle = bo->bo.radeon->handle;
         return TRUE;
     }
 
@@ -305 +444 @@
     return TRUE;
 }
 
-static unsigned eg_tile_split_opp(unsigned tile_split)
-{
-    switch (tile_split) {
-        case 0:     tile_split = 64;    break;
-        case 1:     tile_split = 128;   break;
-        case 2:     tile_split = 256;   break;
-        case 3:     tile_split = 512;   break;
-        default:
-        case 4:     tile_split = 1024;  break;
-        case 5:     tile_split = 2048;  break;
-        case 6:     tile_split = 4096;  break;
-    }
-    return tile_split;
-}
-
 Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
                                       struct radeon_surface *surface)
 {
     ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
     int ihandle = (int)(long)fd_handle;
     uint32_t size = ppix->devKind * ppix->drawable.height;
     Bool ret = FALSE;
 
-    bo = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
+    bo = (struct radeon_buffer *)calloc(1, sizeof(struct radeon_buffer));
     if (!bo)
-        goto error;
+        goto error;
 
-    memset(surface, 0, sizeof(struct radeon_surface));
+#ifdef USE_GLAMOR
+    if (info->use_glamor) {
+        struct gbm_import_fd_data data;
+        uint32_t bo_use = GBM_BO_USE_RENDERING;
+
+        data.format = radeon_get_gbm_format(ppix->drawable.depth,
+                                            ppix->drawable.bitsPerPixel);
+        if (data.format == ~0U)
+            goto error;
 
+        bo->ref_count = 1;
+
+        data.fd = ihandle;
+        data.width = ppix->drawable.width;
+        data.height = ppix->drawable.height;
+        data.stride = ppix->devKind;
+
+        if (ppix->drawable.bitsPerPixel == pScrn->bitsPerPixel)
+            bo_use |= GBM_BO_USE_SCANOUT;
+
+        bo->bo.gbm = gbm_bo_import(info->gbm, GBM_BO_IMPORT_FD, &data, bo_use);
+        if (!bo->bo.gbm)
+            goto error;
+
+        bo->flags |= RADEON_BO_FLAGS_GBM;
+
+        if (!radeon_glamor_create_textured_pixmap(ppix, bo)) {
+            radeon_buffer_unref(&bo);
+            return FALSE;
+        }
+
+        ret = radeon_set_pixmap_bo(ppix, bo);
+        /* radeon_set_pixmap_bo increments ref_count if it succeeds */
+        radeon_buffer_unref(&bo);
+        return ret;
+    }
+#endif
+
+    bo->bo.radeon = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
+    if (!bo)
+        goto error;
+
+    bo->ref_count = 1;
     ret = radeon_set_pixmap_bo(ppix, bo);
     if (!ret)
         goto error;
 
-    if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
+    if (surface) {
+        struct radeon_exa_pixmap_priv *driver_priv;
         uint32_t tiling_flags;
 
-#ifdef USE_GLAMOR
-        if (info->use_glamor) {
-            tiling_flags = radeon_get_pixmap_private(ppix)->tiling_flags;
-        } else
-#endif
-        {
-            struct radeon_exa_pixmap_priv *driver_priv;
-
-            driver_priv = exaGetPixmapDriverPrivate(ppix);
-            tiling_flags = driver_priv->tiling_flags;
-        }
+        driver_priv = exaGetPixmapDriverPrivate(ppix);
+        tiling_flags = driver_priv->tiling_flags;
 
-        surface->npix_x = ppix->drawable.width;
-        surface->npix_y = ppix->drawable.height;
-        surface->npix_z = 1;
-        surface->blk_w = 1;
-        surface->blk_h = 1;
-        surface->blk_d = 1;
-        surface->array_size = 1;
-        surface->bpe = ppix->drawable.bitsPerPixel / 8;
-        surface->nsamples = 1;
-        /* we are requiring a recent enough libdrm version */
-        surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-        surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-        if (tiling_flags & RADEON_TILING_MACRO)
-            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-        else if (tiling_flags & RADEON_TILING_MICRO)
-            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-        else
-            surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-        surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
-        surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
-        surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK);
-        surface->stencil_tile_split = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
-        surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
-        if (radeon_surface_best(info->surf_man, surface)) {
-            ret = FALSE;
-            goto error;
-        }
-        if (radeon_surface_init(info->surf_man, surface)) {
+        if (!radeon_surface_initialize(info, surface, ppix->drawable.width,
+                                       ppix->drawable.height,
+                                       ppix->drawable.bitsPerPixel / 8,
+                                       tiling_flags, 0)) {
             ret = FALSE;
             goto error;
         }
+
         /* we have to post hack the surface to reflect the actual size
            of the shared pixmap */
         surface->level[0].pitch_bytes = ppix->devKind;
@@ -396 +530 @@
     close(ihandle);
     /* we have a reference from the alloc and one from set pixmap bo,
        drop one */
-    radeon_bo_unref(bo);
+    radeon_buffer_unref(&bo);
     return ret;
 }

src/radeon_bo_helper.h

@@ -23 +23 @@
 #ifndef RADEON_BO_HELPER_H
 #define RADEON_BO_HELPER_H 1
 
-extern struct radeon_bo*
+#ifdef USE_GLAMOR
+#include <gbm.h>
+#endif
+
+#define RADEON_BO_FLAGS_GBM     0x1
+
+struct radeon_buffer {
+        union {
+#ifdef USE_GLAMOR
+                struct gbm_bo *gbm;
+#endif
+                struct radeon_bo *radeon;
+        } bo;
+        uint32_t ref_count;
+    uint32_t flags;
+};
+
+extern struct radeon_buffer *
 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
                        int usage_hint, int bitsPerPixel, int *new_pitch,
                        struct radeon_surface *new_surface, uint32_t *new_tiling);
 
 extern void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo);
+
+extern void
 radeon_pixmap_clear(PixmapPtr pixmap);
 
 extern uint32_t
@@ -57 +77 @@
         return drawable->pScreen->GetWindowPixmap((WindowPtr)drawable);
 }
 
+static inline void
+radeon_buffer_ref(struct radeon_buffer *buffer)
+{
+    buffer->ref_count++;
+}
+
+static inline void
+radeon_buffer_unref(struct radeon_buffer **buffer)
+{
+    struct radeon_buffer *buf = *buffer;
+
+    if (!buf)
+        return;
+
+    if (buf->ref_count > 1) {
+        buf->ref_count--;
+        return;
+    }
+
+#ifdef USE_GLAMOR
+    if (buf->flags & RADEON_BO_FLAGS_GBM) {
+        gbm_bo_destroy(buf->bo.gbm);
+    } else
+#endif
+    {
+        radeon_bo_unmap(buf->bo.radeon);
+        radeon_bo_unref(buf->bo.radeon);
+    }
+
+    free(buf);
+    *buffer = NULL;
+}
+
 #endif /* RADEON_BO_HELPER_H */

xf86-video-ati-18.0.1

@@ -79 +79 @@
 static Bool
 radeon_get_flink_name(RADEONEntPtr pRADEONEnt, PixmapPtr pixmap, uint32_t *name)
 {
-    struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);
+    struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap);
     struct drm_gem_flink flink;
 
-    if (bo)
-        return radeon_gem_get_kernel_name(bo, name) == 0;
+    if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM) &&
+        radeon_gem_get_kernel_name(bo->bo.radeon, name) == 0)
+        return TRUE;
 
     if (radeon_get_pixmap_handle(pixmap, &flink.handle)) {
         if (drmIoctl(pRADEONEnt->fd, DRM_IOCTL_GEM_FLINK, &flink) != 0)
@@ -233 +234 @@
                                           flags | RADEON_CREATE_PIXMAP_DRI2);
     }
 
+    if (!pixmap)
+        return NULL;
+
     buffers = calloc(1, sizeof *buffers);
-    if (buffers == NULL)
+    if (!buffers)
         goto error;
 
-    if (pixmap) {
-        if (!info->use_glamor) {
-            info->exa_force_create = TRUE;
-            exaMoveInPixmap(pixmap);
-            info->exa_force_create = FALSE;
-            if (exaGetPixmapDriverPrivate(pixmap) == NULL) {
-                /* this happen if pixmap is non accelerable */
-                goto error;
-            }
-        } else if (is_glamor_pixmap) {
-            pixmap = radeon_glamor_set_pixmap_bo(drawable, pixmap);
-            pixmap->refcnt++;
-        }
-
-        if (!radeon_get_flink_name(pRADEONEnt, pixmap, &buffers->name))
+    if (!info->use_glamor) {
+        info->exa_force_create = TRUE;
+        exaMoveInPixmap(pixmap);
+        info->exa_force_create = FALSE;
+        if (!exaGetPixmapDriverPrivate(pixmap)) {
+            /* this happen if pixmap is non accelerable */
             goto error;
+        }
+    } else if (is_glamor_pixmap) {
+        pixmap = radeon_glamor_set_pixmap_bo(drawable, pixmap);
+        pixmap->refcnt++;
     }
 
+    if (!radeon_get_flink_name(pRADEONEnt, pixmap, &buffers->name))
+        goto error;
+
     privates = calloc(1, sizeof(struct dri2_buffer_priv));
-    if (privates == NULL)
+    if (!privates)
         goto error;
 
     buffers->attachment = attachment;
-    if (pixmap) {
-        buffers->pitch = pixmap->devKind;
-        buffers->cpp = cpp;
-    }
+    buffers->pitch = pixmap->devKind;
+    buffers->cpp = cpp;
     buffers->driverPrivate = privates;
     buffers->format = format;
     buffers->flags = 0; /* not tiled */
@@ -275 +275 @@
 
 error:
     free(buffers);
-    if (pixmap)
-        (*pScreen->DestroyPixmap)(pixmap);
+    (*pScreen->DestroyPixmap)(pixmap);
     return NULL;
 }
 
@@ -338 +337 @@
     Bool vsync;
     Bool translate = FALSE;
     int off_x = 0, off_y = 0;
-    PixmapPtr dst_ppix;
 
-    dst_ppix = dst_private->pixmap;
     src_drawable = &src_private->pixmap->drawable;
     dst_drawable = &dst_private->pixmap->drawable;
 
@@ -357 +354 @@
             dst_drawable = DRI2UpdatePrime(drawable, dest_buffer);
             if (!dst_drawable)
                 return;
-            dst_ppix = (PixmapPtr)dst_drawable;
             if (dst_drawable != drawable)
                 translate = TRUE;
         } else
@@ -381 +377 @@
     (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0);
     ValidateGC(dst_drawable, gc);
 
-    /* If this is a full buffer swap or frontbuffer flush, throttle on the
-     * previous one
-     */
-    if (dst_private->attachment == DRI2BufferFrontLeft) {
-        if (REGION_NUM_RECTS(region) == 1) {
-            BoxPtr extents = REGION_EXTENTS(pScreen, region);
-
-            if (extents->x1 == 0 && extents->y1 == 0 &&
-                extents->x2 == drawable->width &&
-                extents->y2 == drawable->height) {
-                struct radeon_bo *bo = radeon_get_pixmap_bo(dst_ppix);
-
-                if (bo)
-                    radeon_bo_wait(bo);
-            }
-        }
-    }
-
     vsync = info->accel_state->vsync;
-
     /* Driver option "SwapbuffersWait" defines if we vsync DRI2 copy-swaps. */ 
     info->accel_state->vsync = info->swapBuffersWait;
     info->accel_state->force = TRUE;
@@ -743 +720 @@
 {
     struct dri2_buffer_priv *front_priv = front->driverPrivate;
     struct dri2_buffer_priv *back_priv = back->driverPrivate;
-    struct radeon_bo *front_bo, *back_bo;
-    ScreenPtr screen;
-    RADEONInfoPtr info;
+    ScreenPtr screen = draw->pScreen;
+    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen));
     RegionRec region;
     int tmp;
 
@@ -760 +736 @@
     front->name = back->name;
     back->name = tmp;
 
-    /* Swap pixmap bos */
-    front_bo = radeon_get_pixmap_bo(front_priv->pixmap);
-    back_bo = radeon_get_pixmap_bo(back_priv->pixmap);
-    radeon_set_pixmap_bo(front_priv->pixmap, back_bo);
-    radeon_set_pixmap_bo(back_priv->pixmap, front_bo);
-
-    /* Do we need to update the Screen? */
-    screen = draw->pScreen;
-    info = RADEONPTR(xf86ScreenToScrn(screen));
-    if (front_bo == info->front_bo) {
-        radeon_bo_ref(back_bo);
-        radeon_bo_unref(info->front_bo);
-        info->front_bo = back_bo;
-        radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), back_bo);
-    }
+    /* Swap pixmap privates */
+#ifdef USE_GLAMOR
+    if (info->use_glamor) {
+        struct radeon_pixmap *front_pix, *back_pix;
+
+        front_pix = radeon_get_pixmap_private(front_priv->pixmap);
+        back_pix = radeon_get_pixmap_private(back_priv->pixmap);
+        radeon_set_pixmap_private(front_priv->pixmap, back_pix);
+        radeon_set_pixmap_private(back_priv->pixmap, front_pix);
+
+        radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap);
+    } else
+#endif
+    {
+        struct radeon_exa_pixmap_priv driver_priv = *(struct radeon_exa_pixmap_priv*)
+            exaGetPixmapDriverPrivate(front_priv->pixmap);
 
-    radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap);
+        *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(front_priv->pixmap) =
+            *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(back_priv->pixmap);
+        *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(back_priv->pixmap) =
+            driver_priv;
+    }
 
     DamageRegionProcessPending(&front_priv->pixmap->drawable);
 }
@@ -942 +923 @@
     xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, TRUE);
 
     /* Drawable not displayed, make up a value */
-    if (crtc == NULL) {
+    if (!crtc) {
         *ust = 0;
         *msc = 0;
         return TRUE;
@@ -987 +968 @@
 
     scrn = crtc->scrn;
     pRADEONEnt = RADEONEntPriv(scrn);
+    drmmode_crtc = event_info->crtc->driver_private;
     ret = drmmode_get_current_ust(pRADEONEnt->fd, &drm_now);
     if (ret) {
         xf86DrvMsg(scrn->scrnIndex, X_ERROR,
                    "%s cannot get current time\n", __func__);
         if (event_info->drm_queue_seq)
-            radeon_drm_queue_handler(pRADEONEnt->fd, 0, 0, 0,
-                                     (void*)event_info->drm_queue_seq);
+            drmmode_crtc->drmmode->event_context.
+                vblank_handler(pRADEONEnt->fd, 0, 0, 0,
+                               (void*)event_info->drm_queue_seq);
         else
             radeon_dri2_frame_event_handler(crtc, 0, 0, data);
         return 0;
@@ -1002 +985 @@
      * calculate the frame number from current time
      * that would come from CRTC if it were running
      */
-    drmmode_crtc = event_info->crtc->driver_private;
     delta_t = drm_now - (CARD64)drmmode_crtc->dpms_last_ust;
     delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
     delta_seq /= 1000000;
     frame = (CARD64)drmmode_crtc->dpms_last_seq + delta_seq;
     if (event_info->drm_queue_seq)
-        radeon_drm_queue_handler(pRADEONEnt->fd, frame, drm_now / 1000000,
-                                 drm_now % 1000000,
-                                 (void*)event_info->drm_queue_seq);
+        drmmode_crtc->drmmode->event_context.
+            vblank_handler(pRADEONEnt->fd, frame, drm_now / 1000000,
+                           drm_now % 1000000,
+                           (void*)event_info->drm_queue_seq);
     else
         radeon_dri2_frame_event_handler(crtc, frame, drm_now, data);
     return 0;
@@ -1053 +1036 @@
     remainder &= 0xffffffff;
 
     /* Drawable not visible, return immediately */
-    if (crtc == NULL)
+    if (!crtc)
         goto out_complete;
 
     msc_delta = radeon_get_msc_delta(draw, crtc);
@@ -1212 +1195 @@
     radeon_dri2_ref_buffer(back);
 
     /* either off-screen or CRTC not usable... just complete the swap */
-    if (crtc == NULL)
+    if (!crtc)
         goto blit_fallback;
 
     msc_delta = radeon_get_msc_delta(draw, crtc);

xf86-video-ati-18.0.1

@@ -169 +169 @@
 
                         if (priv) {
                                 radeon_set_pixmap_private(pixmap, priv);
+                                pixmap->usage_hint |= RADEON_CREATE_PIXMAP_DRI2;
                                 return pixmap;
                         }
 
@@ -213 +214 @@
 {
         struct radeon_bo *bo;
         int fd;
-
-        bo = radeon_get_pixmap_bo(pixmap);
-        if (!bo) {
 #ifdef USE_GLAMOR
-                ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
-                RADEONInfoPtr info = RADEONPTR(scrn);
+        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+        RADEONInfoPtr info = RADEONPTR(scrn);
 
-                if (info->use_glamor)
-                        return glamor_fd_from_pixmap(screen, pixmap, stride, size);
+        if (info->use_glamor)
+                return glamor_fd_from_pixmap(screen, pixmap, stride, size);
 #endif
 
+        bo = radeon_get_pixmap_bo(pixmap)->bo.radeon;
+        if (!bo) {
                 exaMoveInPixmap(pixmap);
-                bo = radeon_get_pixmap_bo(pixmap);
+                bo = radeon_get_pixmap_bo(pixmap)->bo.radeon;
                 if (!bo)
                         return -1;
         }

src/radeon_drm_queue.c

@@ -40 +40 @@
 
 struct radeon_drm_queue_entry {
     struct xorg_list list;
+    uint64_t usec;
     uint64_t id;
     uintptr_t seq;
     void *data;
@@ -47 +48 @@
     xf86CrtcPtr crtc;
     radeon_drm_handler_proc handler;
     radeon_drm_abort_proc abort;
+    unsigned int frame;
 };
 
 static int radeon_drm_queue_refcnt;
 static struct xorg_list radeon_drm_queue;
+static struct xorg_list radeon_drm_flip_signalled;
+static struct xorg_list radeon_drm_vblank_signalled;
 static uintptr_t radeon_drm_queue_seq;
 
 
 /*
- * Handle a DRM event
+ * Process a DRM event
  */
-void
-radeon_drm_queue_handler(int fd, unsigned int frame, unsigned int sec,
-                         unsigned int usec, void *user_ptr)
+static void
+radeon_drm_queue_handle_one(struct radeon_drm_queue_entry *e)
 {
-        uintptr_t seq = (uintptr_t)user_ptr;
-        struct radeon_drm_queue_entry *e, *tmp;
+    xorg_list_del(&e->list);
+    if (e->handler) {
+        e->handler(e->crtc, e->frame, e->usec, e->data);
+    } else
+        e->abort(e->crtc, e->data);
+    free(e);
+}
+
+static void
+radeon_drm_queue_handler(struct xorg_list *signalled, unsigned int frame,
+                         unsigned int sec, unsigned int usec, void *user_ptr)
+{
+    uintptr_t seq = (uintptr_t)user_ptr;
+    struct radeon_drm_queue_entry *e, *tmp;
 
-        xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
-                if (e->seq == seq) {
-                        xorg_list_del(&e->list);
-                        if (e->handler)
-                                e->handler(e->crtc, frame,
-                                           (uint64_t)sec * 1000000 + usec,
-                                           e->data);
-                        else
-                                e->abort(e->crtc, e->data);
-                        free(e);
-                        break;
-                }
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
+        if (e->seq == seq) {
+            if (!e->handler) {
+                e->abort(e->crtc, e->data);
+                break;
+            }
+
+            xorg_list_del(&e->list);
+            e->usec = (uint64_t)sec * 1000000 + usec;
+            e->frame = frame;
+            xorg_list_append(&e->list, signalled);
+            break;
         }
+    }
+}
+
+/*
+ * Signal a DRM page flip event
+ */
+static void
+radeon_drm_page_flip_handler(int fd, unsigned int frame, unsigned int sec,
+                             unsigned int usec, void *user_ptr)
+{
+    radeon_drm_queue_handler(&radeon_drm_flip_signalled, frame, sec, usec,
+                             user_ptr);
+}
+
+/*
+ * Signal a DRM vblank event
+ */
+static void
+radeon_drm_vblank_handler(int fd, unsigned int frame, unsigned int sec,
+                          unsigned int usec, void *user_ptr)
+{
+    radeon_drm_queue_handler(&radeon_drm_vblank_signalled, frame, sec, usec,
+                             user_ptr);
+}
+
+/*
+ * Handle deferred DRM vblank events
+ *
+ * This function must be called after radeon_drm_wait_pending_flip, once
+ * it's safe to attempt queueing a flip again
+ */
+void
+radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc)
+{
+    drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+    struct radeon_drm_queue_entry *e, *tmp;
+
+    if (drmmode_crtc->wait_flip_nesting_level == 0 ||
+        --drmmode_crtc->wait_flip_nesting_level > 0)
+        return;
+
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) {
+        drmmode_crtc_private_ptr drmmode_crtc = e->crtc->driver_private;
+
+        if (drmmode_crtc->wait_flip_nesting_level == 0)
+            radeon_drm_queue_handle_one(e);
+    }
 }
 
 /*
@@ -150 +212 @@
 {
     struct radeon_drm_queue_entry *e, *tmp;
 
+    if (seq == RADEON_DRM_QUEUE_ERROR)
+        return;
+
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) {
+        if (e->seq == seq) {
+            radeon_drm_abort_one(e);
+            return;
+        }
+    }
+
     xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) {
         if (e->seq == seq) {
             radeon_drm_abort_one(e);
@@ -175 +247 @@
 }
 
 /*
+ * drmHandleEvent wrapper
+ */
+int
+radeon_drm_handle_event(int fd, drmEventContext *event_context)
+{
+    struct radeon_drm_queue_entry *e, *tmp;
+    int r;
+
+    r = drmHandleEvent(fd, event_context);
+
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_flip_signalled, list)
+        radeon_drm_queue_handle_one(e);
+
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) {
+        drmmode_crtc_private_ptr drmmode_crtc = e->crtc->driver_private;
+
+        if (drmmode_crtc->wait_flip_nesting_level == 0)
+            radeon_drm_queue_handle_one(e);
+    }
+
+    return r;
+}
+
+/*
+ * Wait for pending page flip on given CRTC to complete
+ */
+void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc)
+{
+    drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
+    struct radeon_drm_queue_entry *e, *tmp;
+
+    drmmode_crtc->wait_flip_nesting_level++;
+
+    xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_flip_signalled, list)
+        radeon_drm_queue_handle_one(e);
+
+    while (drmmode_crtc->flip_pending
+           && radeon_drm_handle_event(pRADEONEnt->fd,
+                                          &drmmode_crtc->drmmode->event_context) > 0);
+}
+
+/*
  * Initialize the DRM event queue
  */
 void
-radeon_drm_queue_init()
+radeon_drm_queue_init(ScrnInfoPtr scrn)
 {
+    RADEONInfoPtr info = RADEONPTR(scrn);
+    drmmode_ptr drmmode = &info->drmmode;
+
+    drmmode->event_context.version = 2;
+    drmmode->event_context.vblank_handler = radeon_drm_vblank_handler;
+    drmmode->event_context.page_flip_handler = radeon_drm_page_flip_handler;
+
     if (radeon_drm_queue_refcnt++)
         return;
 
     xorg_list_init(&radeon_drm_queue);
+    xorg_list_init(&radeon_drm_flip_signalled);
+    xorg_list_init(&radeon_drm_vblank_signalled);
 }
 
 /*

src/radeon_drm_queue.h

@@ -40 +40 @@
                                         uint64_t usec, void *data);
 typedef void (*radeon_drm_abort_proc)(xf86CrtcPtr crtc, void *data);
 
-void radeon_drm_queue_handler(int fd, unsigned int frame,
-                              unsigned int tv_sec, unsigned int tv_usec,
-                              void *user_ptr);
+void radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc);
 uintptr_t radeon_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
                                  uint64_t id, void *data,
                                  radeon_drm_handler_proc handler,
@@ -50 +48 @@
 void radeon_drm_abort_client(ClientPtr client);
 void radeon_drm_abort_entry(uintptr_t seq);
 void radeon_drm_abort_id(uint64_t id);
-void radeon_drm_queue_init();
+int radeon_drm_handle_event(int fd, drmEventContext *event_context);
+void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc);
+void radeon_drm_queue_init(ScrnInfoPtr scrn);
 void radeon_drm_queue_close(ScrnInfoPtr scrn);
 
 #endif /* _RADEON_DRM_QUEUE_H_ */

xf86-video-ati-18.0.1

@@ -150 +150 @@
  */
 Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t)
 {
-        if (t == NULL)
+        if (!t)
                 return TRUE;
         /* the shaders don't handle scaling either */
         return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1);
@@ -184 +184 @@
         return FALSE;
 
     /* if we have more refs than just the BO then flush */
-    if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+    if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
         flush = TRUE;
 
         if (can_fail) {
-            possible_domains = radeon_bo_get_src_domain(driver_priv->bo);
+            possible_domains = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
             if (possible_domains == RADEON_GEM_DOMAIN_VRAM)
                 return FALSE; /* use DownloadFromScreen */
         }
@@ -196 +196 @@
 
     /* if the BO might end up in VRAM, prefer DownloadFromScreen */
     if (can_fail && (possible_domains & RADEON_GEM_DOMAIN_VRAM)) {
-        radeon_bo_is_busy(driver_priv->bo, &current_domain);
+        radeon_bo_is_busy(driver_priv->bo->bo.radeon, &current_domain);
 
         if (current_domain & possible_domains) {
             if (current_domain == RADEON_GEM_DOMAIN_VRAM)
@@ -209 +209 @@
         radeon_cs_flush_indirect(pScrn);
     
     /* flush IB */
-    ret = radeon_bo_map(driver_priv->bo, 1);
+    ret = radeon_bo_map(driver_priv->bo->bo.radeon, 1);
     if (ret) {
       FatalError("failed to map pixmap %d\n", ret);
       return FALSE;
     }
     driver_priv->bo_mapped = TRUE;
 
-    pPix->devPrivate.ptr = driver_priv->bo->ptr;
+    pPix->devPrivate.ptr = driver_priv->bo->bo.radeon->ptr;
 
     return TRUE;
 }
@@ -229 +229 @@
     if (!driver_priv || !driver_priv->bo_mapped)
         return;
 
-    radeon_bo_unmap(driver_priv->bo);
+    radeon_bo_unmap(driver_priv->bo->bo.radeon);
     driver_priv->bo_mapped = FALSE;
     pPix->devPrivate.ptr = NULL;
 }
 
 
-void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align)
-{
-    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
-    RADEONInfoPtr info = RADEONPTR(pScrn);
-    struct radeon_exa_pixmap_priv *new_priv;
-
-    if (size != 0 && !info->exa_force_create &&
-        info->exa_pixmaps == FALSE)
-        return NULL;
-            
-    new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
-    if (!new_priv)
-        return NULL;
-
-    if (size == 0)
-        return new_priv;
-
-    new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, align,
-                                  RADEON_GEM_DOMAIN_VRAM, 0);
-    if (!new_priv->bo) {
-        free(new_priv);
-        ErrorF("Failed to alloc memory\n");
-        return NULL;
-    }
-    
-    return new_priv;
-
-}
-
 void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
                              int depth, int usage_hint, int bitsPerPixel,
                              int *new_pitch)
@@ -306 +277 @@
     if (!driverPriv)
       return;
 
-    if (driver_priv->bo)
-        radeon_bo_unref(driver_priv->bo);
+    radeon_buffer_unref(&driver_priv->bo);
     drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL);
     free(driverPriv);
 }
@@ -316 +286 @@
 {
     struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix);
 
-    if (!radeon_share_pixmap_backing(driver_priv->bo, fd_handle))
+    if (!radeon_share_pixmap_backing(driver_priv->bo->bo.radeon, fd_handle))
         return FALSE;
 
     driver_priv->shared = TRUE;

src/radeon_exa_funcs.c

@@ -138 +138 @@
     radeon_cs_space_reset_bos(info->cs);
 
     driver_priv = exaGetPixmapDriverPrivate(pPix);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      RADEON_GEM_DOMAIN_VRAM);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret)
@@ -146 +147 @@
 
     driver_priv = exaGetPixmapDriverPrivate(pPix);
     if (driver_priv) {
-        info->state_2d.dst_bo = driver_priv->bo;
+        info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
         info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
     }
 
@@ -256 +257 @@
     radeon_cs_space_reset_bos(info->cs);
 
     driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
-    info->state_2d.src_bo = driver_priv->bo;
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon,
+                                      RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+    info->state_2d.src_bo = driver_priv->bo->bo.radeon;
 
     driver_priv = exaGetPixmapDriverPrivate(pDst);
-    info->state_2d.dst_bo = driver_priv->bo;
+    info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
     info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, info->state_2d.dst_domain);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      info->state_2d.dst_domain);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret)
@@ -328 +331 @@
 
     if (src_bo && dst_bo) {
         BEGIN_ACCEL_RELOC(6, 2);
-    } else if (src_bo && dst_bo == NULL) {
+    } else if (src_bo && !dst_bo) {
         BEGIN_ACCEL_RELOC(6, 1);
     } else {
         BEGIN_RING(2*6);
@@ -389 +392 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pDst);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
 #if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -404 +407 @@
 #endif
 
     /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
-    copy_dst = driver_priv->bo;
+    copy_dst = driver_priv->bo->bo.radeon;
     copy_pitch = pDst->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+        if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
             flush = FALSE;
-            if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+            if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
                 !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
                 goto copy;
         }
@@ -420 +423 @@
 
     size = scratch_pitch * h;
     scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
     radeon_cs_space_reset_bos(info->cs);
@@ -446 +449 @@
     r = TRUE;
     size = w * bpp / 8;
     dst = copy_dst->ptr;
-    if (copy_dst == driver_priv->bo)
+    if (copy_dst == driver_priv->bo->bo.radeon)
         dst += y * copy_pitch + x * bpp / 8;
     for (i = 0; i < h; i++) {
         RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap);
@@ -458 +461 @@
         RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype);
         RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset);
         RADEON_SWITCH_TO_2D();
-        RADEONBlitChunk(pScrn, scratch, driver_priv->bo, datatype, scratch_pitch << 16,
+        RADEONBlitChunk(pScrn, scratch, driver_priv->bo->bo.radeon, datatype, scratch_pitch << 16,
                         dst_pitch_offset, 0, 0, x, y, w, h,
                         RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_VRAM);
     }
@@ -493 +496 @@
         return FALSE;
 
     driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
         return FALSE;
 
 #if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -508 +511 @@
 #endif
 
     /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
-    copy_src = driver_priv->bo;
+    copy_src = driver_priv->bo->bo.radeon;
     copy_pitch = pSrc->devKind;
     if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-        if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
-            src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+        if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
+            src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
             if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
                 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
                 src_domain = 0;
@@ -521 +524 @@
         }
 
         if (!src_domain)
-            radeon_bo_is_busy(driver_priv->bo, &src_domain);
+            radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);
 
         if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
             goto copy;
     }
     size = scratch_pitch * h;
     scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
-    if (scratch == NULL) {
+    if (!scratch) {
         goto copy;
     }
     radeon_cs_space_reset_bos(info->cs);
@@ -541 +544 @@
     RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype);
     RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset);
     RADEON_SWITCH_TO_2D();
-    RADEONBlitChunk(pScrn, driver_priv->bo, scratch, datatype, src_pitch_offset,
-                    scratch_pitch << 16, x, y, 0, 0, w, h,
+    RADEONBlitChunk(pScrn, driver_priv->bo->bo.radeon, scratch, datatype,
+                    src_pitch_offset, scratch_pitch << 16, x, y, 0, 0, w, h,
                     RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT,
                     RADEON_GEM_DOMAIN_GTT);
     copy_src = scratch;
@@ -561 +564 @@
     }
     r = TRUE;
     w *= bpp / 8;
-    if (copy_src == driver_priv->bo)
+    if (copy_src == driver_priv->bo->bo.radeon)
         size = y * copy_pitch + x * bpp / 8;
     else
         size = 0;
@@ -581 +584 @@
 {
     RINFO_FROM_SCREEN(pScreen);
 
-    if (info->accel_state->exa == NULL) {
+    if (!info->accel_state->exa) {
         xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
         return FALSE;
     }
@@ -638 +641 @@
     }
 #endif
 
-    info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
     info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
     info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
     info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;

src/radeon_exa_render.c

@@ -630 +630 @@
         return FALSE;
     pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
 
-    if (pMask != NULL) {
+    if (pMask) {
         if (!R100TextureSetup(pMaskPicture, pMask, 1))
             return FALSE;
         pp_cntl |= RADEON_TEX_1_ENABLE;
@@ -992 +992 @@
         return FALSE;
     pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
 
-    if (pMask != NULL) {
+    if (pMask) {
         if (!R200TextureSetup(pMaskPicture, pMask, 1))
             return FALSE;
         pp_cntl |= RADEON_TEX_1_ENABLE;
@@ -1484 +1484 @@
         return FALSE;
     txenable = R300_TEX_0_ENABLE;
 
-    if (pMask != NULL) {
+    if (pMask) {
         if (!R300TextureSetup(pMaskPicture, pMask, 1))
             return FALSE;
         txenable |= R300_TEX_1_ENABLE;

src/radeon_exa_shared.c

@@ -129 +129 @@
     struct radeon_bo *bo;
     exaMoveInPixmap(pPix);
 
-    bo = radeon_get_pixmap_bo(pPix);
+    bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
 
     if (radeon_bo_map(bo, 1)) {
         pScreen->DestroyPixmap(pPix);

src/radeon_exa_shared.h

@@ -66 +66 @@
 {
     struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
 
-    radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
+    radeon_cs_space_add_persistent_bo(cs, driver_priv->bo->bo.radeon,
+                                      read_domains, write_domain);
 }
 
 extern void radeon_ib_discard(ScrnInfoPtr pScrn);

xf86-video-ati-18.0.1

@@ -50 +50 @@
 Bool
 radeon_glamor_create_screen_resources(ScreenPtr screen)
 {
+        PixmapPtr screen_pixmap = screen->GetScreenPixmap(screen);
         ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
         RADEONInfoPtr info = RADEONPTR(scrn);
 
@@ -61 +62 @@
                 return FALSE;
 #endif
 
-        if (!glamor_egl_create_textured_screen(screen,
-                                               info->front_bo->handle,
-                                               scrn->displayWidth *
-                                               info->pixel_bytes))
-                return FALSE;
-
-        return TRUE;
+        return radeon_glamor_create_textured_pixmap(screen_pixmap,
+                                                    info->front_buffer);
 }
 
 
@@ -136 +132 @@
         }
 #endif
 
+        info->gbm = gbm_create_device(pRADEONEnt->fd);
+        if (!info->gbm) {
+                xf86DrvMsg(scrn->scrnIndex, X_ERROR,
+                           "gbm_create_device returned NULL\n");
+                return FALSE;
+        }
+
         /* Load glamor module */
         if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) {
                 version = xf86GetModuleVersion(glamor_module);
@@ -164 +167 @@
 }
 
 Bool
-radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv)
+radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo)
 {
-        return glamor_egl_create_textured_pixmap(pixmap, priv->bo->handle,
-                                                 pixmap->devKind);
+        ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
+        RADEONInfoPtr info = RADEONPTR(scrn);
+
+        if (!info->use_glamor)
+                return TRUE;
+
+        if (bo->flags & RADEON_BO_FLAGS_GBM) {
+                return glamor_egl_create_textured_pixmap_from_gbm_bo(pixmap,
+                                                                     bo->bo.gbm
+#if XORG_VERSION_CURRENT > XORG_VERSION_NUMERIC(1,19,99,903,0)
+                                                                     , FALSE
+#endif
+                                                                     );
+        } else {
+                return glamor_egl_create_textured_pixmap(pixmap,
+                                                         bo->bo.radeon->handle,
+                                                         pixmap->devKind);
+        }
 }
 
 static Bool radeon_glamor_destroy_pixmap(PixmapPtr pixmap)
@@ -179 +198 @@
 #endif
 
         if (pixmap->refcnt == 1) {
-                if (pixmap->devPrivate.ptr) {
-                        struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);
-
-                        if (bo)
-                                radeon_bo_unmap(bo);
-                }
-
 #ifdef HAVE_GLAMOR_EGL_DESTROY_TEXTURED_PIXMAP
                 glamor_egl_destroy_textured_pixmap(pixmap);
 #endif
@@ -214 +226 @@
         struct radeon_pixmap *priv;
         PixmapPtr pixmap, new_pixmap = NULL;
 
+        if (!xf86GetPixFormat(scrn, depth))
+                return NULL;
+
         if (!RADEON_CREATE_PIXMAP_SHARED(usage)) {
                 if (info->shadow_primary) {
                         if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP)
@@ -242 +257 @@
                 int stride;
 
                 priv = calloc(1, sizeof (struct radeon_pixmap));
-                if (priv == NULL)
+                if (!priv)
                         goto fallback_pixmap;
 
                 priv->bo = radeon_alloc_pixmap_bo(scrn, w, h, depth, usage,
                                                   pixmap->drawable.bitsPerPixel,
-                                                  &stride,
-                                                  &priv->surface,
+                                                  &stride, NULL,
                                                   &priv->tiling_flags);
                 if (!priv->bo)
                         goto fallback_priv;
@@ -257 +271 @@
 
                 screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL);
 
-                if (!radeon_glamor_create_textured_pixmap(pixmap, priv))
+                if (!radeon_glamor_create_textured_pixmap(pixmap, priv->bo))
                         goto fallback_glamor;
 
                 pixmap->devPrivate.ptr = NULL;
@@ -287 +301 @@
          * afterwards.
          */
         new_pixmap = glamor_create_pixmap(screen, w, h, depth, usage);
-        radeon_bo_unref(priv->bo);
+        radeon_buffer_unref(&priv->bo);
 fallback_priv:
         free(priv);
 fallback_pixmap:
@@ -388 +402 @@
 {
         ScreenPtr screen = pixmap->drawable.pScreen;
         ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
-        struct radeon_surface surface;
-        struct radeon_pixmap *priv;
 
-        if (!radeon_set_shared_pixmap_backing(pixmap, handle, &surface))
+        if (!radeon_set_shared_pixmap_backing(pixmap, handle, NULL))
                 return FALSE;
 
-        priv = radeon_get_pixmap_private(pixmap);
-        priv->surface = surface;
-
-        if (!radeon_glamor_create_textured_pixmap(pixmap, priv)) {
+        if (!radeon_glamor_create_textured_pixmap(pixmap,
+                                                  radeon_get_pixmap_bo(pixmap))) {
                 xf86DrvMsg(scrn->scrnIndex, X_ERROR,
                            "Failed to get PRIME drawable for glamor pixmap.\n");
                 return FALSE;

xf86-video-ati-18.0.1

@@ -33 +33 @@
 
 #ifdef USE_GLAMOR
 
+#ifndef HAVE_GLAMOR_FINISH
+#include <GL/gl.h>
+#endif
+
+#include <gbm.h>
+
 #define GLAMOR_FOR_XORG  1
 #include <glamor.h>
 
@@ -65 +71 @@
 Bool radeon_glamor_create_screen_resources(ScreenPtr screen);
 void radeon_glamor_free_screen(int scrnIndex, int flags);
 
-Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv);
+Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo);
 void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
 PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap);
 
 XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt);
 
+static inline void
+radeon_glamor_finish(ScrnInfoPtr scrn)
+{
+        RADEONInfoPtr info = RADEONPTR(scrn);
+
+#if HAVE_GLAMOR_FINISH
+        glamor_finish(scrn->pScreen);
+#else
+        glamor_block_handler(scrn->pScreen);
+        glFinish();
+#endif
+
+        info->gpu_flushed++;
+}
+
 #else
 
 static inline Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { return FALSE; }
@@ -79 +100 @@
 static inline Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { return FALSE; }
 static inline void radeon_glamor_free_screen(int scrnIndex, int flags) { }
 
-static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_pixmap *priv) { return TRUE; }
+static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo) { return TRUE; }
 
 static inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {}
 static inline PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap) { return pixmap; }
@@ -87 +108 @@
 static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
 
 static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; }
+
+static inline void radeon_glamor_finish(ScrnInfoPtr pScrn) { }
+
 #endif
 
 #endif /* RADEON_GLAMOR_H */

src/radeon_glamor_wrappers.c

@@ -55 +55 @@
                                  PixmapPtr pixmap, struct radeon_pixmap *priv,
                                  Bool need_sync)
 {
-        struct radeon_bo *bo = priv->bo;
+        struct radeon_buffer *bo = priv->bo;
         int ret;
 
-        /* When falling back to swrast, flush all pending operations */
-        if (need_sync) {
-                glamor_block_handler(scrn->pScreen);
-                info->gpu_flushed++;
-        }
-
         if (!pixmap->devPrivate.ptr) {
-                ret = radeon_bo_map(bo, 1);
+                /* When falling back to swrast, flush all pending operations */
+                if (need_sync) {
+                        glamor_block_handler(scrn->pScreen);
+                        info->gpu_flushed++;
+                }
+
+                ret = radeon_bo_map(bo->bo.radeon, 1);
                 if (ret) {
                         xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                                    "%s: bo map (tiling_flags %d) failed: %s\n",
@@ -75 +75 @@
                         return FALSE;
                 }
 
-                pixmap->devPrivate.ptr = bo->ptr;
-                info->gpu_synced = info->gpu_flushed;
-        } else if (need_sync) {
-                radeon_bo_wait(bo);
-                info->gpu_synced = info->gpu_flushed;
-        }
+                pixmap->devPrivate.ptr = bo->bo.radeon->ptr;
+        } else if (need_sync)
+                radeon_finish(scrn, bo);
+
+        info->gpu_synced = info->gpu_flushed;
 
         return TRUE;
 }
@@ -133 +132 @@
 static Bool
 radeon_glamor_prepare_access_gpu(struct radeon_pixmap *priv)
 {
-        return priv != NULL;
+        return !!priv;
 }
 
 static void
@@ -202 +201 @@
         PixmapPtr pixmap;
         struct radeon_pixmap *priv;
 
-        if (picture->pDrawable == NULL)
+        if (!picture->pDrawable)
                 return TRUE;
 
         pixmap = get_drawable_pixmap(picture->pDrawable);

xf86-video-ati-18.0.1

@@ -83 +83 @@
 #include "radeon_dri2.h"
 #include "drmmode_display.h"
 #include "radeon_surface.h"
+#include "radeon_bo_helper.h"
 
                                 /* Render support */
 #ifdef RENDER
@@ -300 +301 @@
 #define CURSOR_WIDTH_CIK        128
 #define CURSOR_HEIGHT_CIK       128
 
-
 #ifdef USE_GLAMOR
 
 struct radeon_pixmap {
-        struct radeon_surface surface;
-
         uint_fast32_t gpu_read;
         uint_fast32_t gpu_write;
 
-        struct radeon_bo *bo;
+        struct radeon_buffer *bo;
         struct drmmode_fb *fb;
 
         uint32_t tiling_flags;
@@ -335 +333 @@
 
 
 struct radeon_exa_pixmap_priv {
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
     struct drmmode_fb *fb;
     uint32_t tiling_flags;
     struct radeon_surface surface;
@@ -569 +567 @@
 
     void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 
     struct radeon_2d_state state_2d;
-    struct radeon_bo *front_bo;
+    struct radeon_buffer *front_buffer;
     struct radeon_bo_manager *bufmgr;
     struct radeon_cs_manager *csm;
     struct radeon_cs *cs;
@@ -608 +606 @@
     unsigned hwcursor_disabled;
 
 #ifdef USE_GLAMOR
+    struct gbm_device *gbm;
+
     struct {
         CreateGCProcPtr SavedCreateGC;
         RegionPtr (*SavedCopyArea)(DrawablePtr, DrawablePtr, GCPtr, int, int,
@@ -645 +645 @@
 extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn);
 
 /* radeon_bo_helper.c */
+extern Bool
+radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
+                          int width, int height, int cpp, uint32_t tiling_flags,
+                          int usage_hint);
+
 extern Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle);
 
 /* radeon_commonfuncs.c */
@@ -703 +708 @@
 
 static inline struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix)
 {
-#ifdef USE_GLAMOR
-    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
+    struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
 
-    if (info->use_glamor) {
-        struct radeon_pixmap *priv;
-        priv = radeon_get_pixmap_private(pPix);
-        return priv ? &priv->surface : NULL;
-    } else
-#endif
-    {
-        struct radeon_exa_pixmap_priv *driver_priv;
-        driver_priv = exaGetPixmapDriverPrivate(pPix);
-        return &driver_priv->surface;
-    }
-
-    return NULL;
+    return &driver_priv->surface;
 }
 
 uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix);
 
-static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
+static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_buffer *bo)
 {
     ScrnInfoPtr scrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
@@ -734 +726 @@
         struct radeon_pixmap *priv;
 
         priv = radeon_get_pixmap_private(pPix);
-        if (priv == NULL && bo == NULL)
+        if (!priv && !bo)
             return TRUE;
 
         if (priv) {
@@ -742 +734 @@
                 if (priv->bo == bo)
                     return TRUE;
 
-                radeon_bo_unref(priv->bo);
+                radeon_buffer_unref(&priv->bo);
+                priv->handle_valid = FALSE;
             }
 
             drmmode_fb_reference(pRADEONEnt->fd, &priv->fb, NULL);
@@ -754 +747 @@
         }
 
         if (bo) {
-            uint32_t pitch;
-
             if (!priv) {
                 priv = calloc(1, sizeof (struct radeon_pixmap));
                 if (!priv)
                     return FALSE;
             }
 
-            radeon_bo_ref(bo);
+            radeon_buffer_ref(bo);
             priv->bo = bo;
-
-            radeon_bo_get_tiling(bo, &priv->tiling_flags, &pitch);
         }
 
         radeon_set_pixmap_private(pPix, priv);
+        radeon_get_pixmap_tiling_flags(pPix);
         return TRUE;
     } else
 #endif /* USE_GLAMOR */
@@ -779 +769 @@
         if (driver_priv) {
             uint32_t pitch;
 
-            if (driver_priv->bo)
-                radeon_bo_unref(driver_priv->bo);
-
+            radeon_buffer_unref(&driver_priv->bo);
             drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL);
 
-            radeon_bo_ref(bo);
+            radeon_buffer_ref(bo);
             driver_priv->bo = bo;
 
-            radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch);
+            radeon_bo_get_tiling(bo->bo.radeon, &driver_priv->tiling_flags,
+                                 &pitch);
             return TRUE;
         }
 
@@ -795 +784 @@
     }
 }
 
-static inline struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
+static inline struct radeon_buffer *radeon_get_pixmap_bo(PixmapPtr pPix)
 {
 #ifdef USE_GLAMOR
     RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
@@ -905 +894 @@
     return *fb_ptr;
 }
 
+
 #define CP_PACKET0(reg, n)                                              \
         (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET1(reg0, reg1)                                          \
@@ -1013 +1003 @@
 #define EMIT_OFFSET(reg, value, pPix, rd, wd) do {              \
     driver_priv = exaGetPixmapDriverPrivate(pPix);              \
     OUT_RING_REG((reg), (value));                               \
-    OUT_RING_RELOC(driver_priv->bo, (rd), (wd));                        \
+    OUT_RING_RELOC(driver_priv->bo->bo.radeon, (rd), (wd));     \
     } while(0)
 
 #define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0)
@@ -1027 +1017 @@
 #define EMIT_COLORPITCH(reg, value, pPix) do {                  \
     driver_priv = exaGetPixmapDriverPrivate(pPix);                      \
     OUT_RING_REG((reg), value);                                 \
-    OUT_RING_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);         \
+    OUT_RING_RELOC(driver_priv->bo->bo.radeon, 0, RADEON_GEM_DOMAIN_VRAM);      \
 } while(0)
 
 static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)

xf86-video-ati-18.0.1

@@ -212 +212 @@
             info->accel_state = NULL;
         }
 
+#ifdef USE_GLAMOR
+        if (info->gbm)
+            gbm_device_destroy(info->gbm);
+#endif
+
         pEnt = info->pEnt;
         free(pScrn->driverPrivate);
         pScrn->driverPrivate = NULL;
@@ -254 +259 @@
     stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
     *size = stride;
 
-    return ((uint8_t *)info->front_bo->ptr + row * stride + offset);
+    return ((uint8_t *)info->front_buffer->bo.radeon->ptr + row * stride + offset);
 }
 
 static void
@@ -326 +331 @@
     ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info   = RADEONPTR(pScrn);
     PixmapPtr pixmap;
-    struct radeon_surface *surface;
 
     pScreen->CreateScreenResources = info->CreateScreenResources;
     if (!(*pScreen->CreateScreenResources)(pScreen))
@@ -360 +364 @@
     }
 
     if (info->dri2.enabled || info->use_glamor) {
-        if (info->front_bo) {
+        if (info->front_buffer) {
             PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
-            if (!radeon_set_pixmap_bo(pPix, info->front_bo))
+            if (!radeon_set_pixmap_bo(pPix, info->front_buffer))
                 return FALSE;
-            surface = radeon_get_pixmap_surface(pPix);
-            if (surface) {
-                *surface = info->front_surface;
-            }
+
+            if (info->surf_man && !info->use_glamor)
+                *radeon_get_pixmap_surface(pPix) = info->front_surface;
         }
     }
 
@@ -523 +526 @@
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
     drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
 
-    drmmode_crtc->scanout_update_pending = FALSE;
+    drmmode_crtc->scanout_update_pending = 0;
     drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,
                          NULL);
 }
@@ -538 +541 @@
     drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb,
                          drmmode_crtc->flip_pending);
     radeon_scanout_flip_abort(crtc, event_data);
-
-#ifdef HAVE_PRESENT_H
-    if (drmmode_crtc->present_vblank_event_id) {
-        present_event_notify(drmmode_crtc->present_vblank_event_id,
-                             drmmode_crtc->present_vblank_usec,
-                             drmmode_crtc->present_vblank_msc);
-        drmmode_crtc->present_vblank_event_id = 0;
-    }
-#endif
 }
 
 
@@ -608 +602 @@
 {
     drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
 
-    drmmode_crtc->scanout_update_pending = FALSE;
+    drmmode_crtc->scanout_update_pending = 0;
 }
 
 void
@@ -636 +630 @@
 {
     ScreenPtr master_screen = radeon_dirty_master(dirty);
 
-    return master_screen->SyncSharedPixmap != NULL;
+    return !!master_screen->SyncSharedPixmap;
 }
 
 static Bool
@@ -644 +638 @@
 {
     ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen;
 
-    return slave_screen->SyncSharedPixmap != NULL;
+    return !!slave_screen->SyncSharedPixmap;
 }
 
 static void
@@ -749 +743 @@
     drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
 
     radeon_prime_scanout_do_update(crtc, 0);
-    drmmode_crtc->scanout_update_pending = FALSE;
+    drmmode_crtc->scanout_update_pending = 0;
 }
 
 static void
@@ -790 +784 @@
         return;
     }
 
-    drmmode_crtc->scanout_update_pending = TRUE;
+    drmmode_crtc->scanout_update_pending = drm_queue_seq;
 }
 
 static void
@@ -848 +842 @@
     }
 
     drmmode_crtc->scanout_id = scanout_id;
-    drmmode_crtc->scanout_update_pending = TRUE;
+    drmmode_crtc->scanout_update_pending = drm_queue_seq;
 }
 
 static void
@@ -987 +981 @@
         FreeScratchGC(gc);
     }
 
-    radeon_cs_flush_indirect(scrn);
-
     info->accel_state->force = force;
 
     return TRUE;
@@ -999 +991 @@
 {
     drmmode_crtc_private_ptr drmmode_crtc = event_data;
 
-    drmmode_crtc->scanout_update_pending = FALSE;
+    drmmode_crtc->scanout_update_pending = 0;
 }
 
 static void
@@ -1015 +1007 @@
         drmmode_crtc->dpms_mode == DPMSModeOn) {
         if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id,
                                      screen->GetWindowPixmap(screen->root),
-                                     region->extents))
+                                     region->extents)) {
+            radeon_cs_flush_indirect(crtc->scrn);
             RegionEmpty(region);
+        }
     }
 
     radeon_scanout_update_abort(crtc, event_data);
@@ -1074 +1068 @@
         return;
     }
 
-    drmmode_crtc->scanout_update_pending = TRUE;
+    drmmode_crtc->scanout_update_pending = drm_queue_seq;
 }
 
 static void
@@ -1098 +1092 @@
                                   pScreen->GetWindowPixmap(pScreen->root),
                                   region->extents))
         return;
+
+    radeon_cs_flush_indirect(scrn);
     RegionEmpty(region);
 
     drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
@@ -1139 +1135 @@
     }
 
     drmmode_crtc->scanout_id = scanout_id;
-    drmmode_crtc->scanout_update_pending = TRUE;
+    drmmode_crtc->scanout_update_pending = drm_queue_seq;
 }
 
 static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL)
@@ -1162 +1158 @@
             xf86CrtcPtr crtc = xf86_config->crtc[c];
             drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
 
+            if (drmmode_crtc->rotate.pixmap)
+                continue;
+
             if (drmmode_crtc->tear_free)
                 radeon_scanout_flip(pScreen, info, crtc);
             else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap)
@@ -1681 +1680 @@
     pScreen->WindowExposures(pWin, pRegion);
 #endif
 
-    radeon_cs_flush_indirect(pScrn);
-    radeon_bo_wait(info->front_bo);
+    radeon_finish(pScrn, info->front_buffer);
     drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE);
 }
 
@@ -1762 +1760 @@
     info->dri2.available = FALSE;
     info->dri2.enabled = FALSE;
     info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd);
-    if (info->dri2.pKernelDRMVersion == NULL) {
+    if (!info->dri2.pKernelDRMVersion) {
         xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
                    "RADEONDRIGetVersion failed to get the DRM version\n");
         return FALSE;
@@ -1782 +1780 @@
         return FALSE;
     }
 
-    radeon_drm_queue_init();
+    radeon_drm_queue_init(pScrn);
 
     info->allowColorTiling2D = FALSE;
 
@@ -1917 +1915 @@
             xf86OutputPtr output = xf86_config->output[i];
 
             /* XXX: double check crtc mode */
-            if ((output->probed_modes != NULL) && (output->crtc == NULL))
+            if (output->probed_modes && !output->crtc)
                 output->crtc = xf86_config->crtc[0];
         }
     }
@@ -1980 +1978 @@
         if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
     }
 
-    if (pScrn->modes == NULL
+    if (!pScrn->modes
 #ifdef XSERVER_PLATFORM_BUS
         && !pScrn->is_gpu
 #endif
@@ -2091 +2089 @@
     unblank = xf86IsUnblank(mode);
     if (unblank) SetTimeSinceLastInputEvent();
 
-    if ((pScrn != NULL) && pScrn->vtSema) {
+    if (pScrn && pScrn->vtSema) {
         if (unblank)
             RADEONUnblank(pScrn);
         else
@@ -2228 +2226 @@
     if (info->r600_shadow_fb == FALSE)
         info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
 
-    info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd);
+    if (info->ChipFamily >= CHIP_FAMILY_R600) {
+        info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd);
+
+        if (!info->surf_man) {
+            xf86DrvMsg(pScreen->myNum, X_ERROR,
+                       "Failed to initialize surface manager\n");
+            return FALSE;
+        }
+    }
+
     if (!info->bufmgr)
         info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd);
     if (!info->bufmgr) {
@@ -2261 +2268 @@
         xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n");
         return FALSE;
     }
-    front_ptr = info->front_bo->ptr;
+
+    if (!(info->front_buffer->flags & RADEON_BO_FLAGS_GBM))
+        front_ptr = info->front_buffer->bo.radeon->ptr;
+    else
+        front_ptr = NULL;
 
     if (info->r600_shadow_fb) {
         info->fb_shadow = calloc(1,
                                  pScrn->displayWidth * pScrn->virtualY *
                                  ((pScrn->bitsPerPixel + 7) >> 3));
-        if (info->fb_shadow == NULL) {
+        if (!info->fb_shadow) {
             xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
                        "Failed to allocate shadow framebuffer\n");
             return FALSE;
@@ -2470 +2481 @@
     if (info->r600_shadow_fb) {
         int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0);
         struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0,
-                                                    info->front_bo->size,
+                                                    pScrn->displayWidth *
+                                                    info->pixel_bytes *
+                                                    pScrn->virtualY,
                                                     base_align,
                                                     RADEON_GEM_DOMAIN_VRAM, 0);
 
         if (front_bo) {
             if (radeon_bo_map(front_bo, 1) == 0) {
                 memset(front_bo->ptr, 0, front_bo->size);
-                radeon_bo_unref(info->front_bo);
-                info->front_bo = front_bo;
+                radeon_bo_unref(info->front_buffer->bo.radeon);
+                info->front_buffer->bo.radeon = front_bo;
             } else {
                 radeon_bo_unref(front_bo);
                 front_bo = NULL;
@@ -2576 +2589 @@
                     radeon_pixmap_get_fb(black_scanout.pixmap);
 
                 radeon_pixmap_clear(black_scanout.pixmap);
-                radeon_cs_flush_indirect(pScrn);
-                radeon_bo_wait(black_scanout.bo);
+                radeon_finish(pScrn, black_scanout.bo);
 
                 for (i = 0; i < xf86_config->num_crtc; i++) {
                     crtc = xf86_config->crtc[i];
@@ -2626 +2638 @@
 
         pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen), None, pRADEONEnt);
     } else {
-        memset(info->front_bo->ptr, 0, info->front_bo->size);
+        memset(info->front_buffer->bo.radeon->ptr, 0,
+               pScrn->displayWidth * info->pixel_bytes * pScrn->virtualY);
     }
 
     TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen);
@@ -2664 +2677 @@
     RADEONInfoPtr info = RADEONPTR(pScrn);
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     int cpp = info->pixel_bytes;
-    uint32_t screen_size;
-    int pitch, base_align;
+    int pitch;
     uint32_t tiling_flags = 0;
-    struct radeon_surface surface;
 
-    if (info->accel_state->exa != NULL) {
+    if (info->accel_state->exa) {
         xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
         return FALSE;
     }
     if (!info->use_glamor && info->r600_shadow_fb == FALSE) {
         info->accel_state->exa = exaDriverAlloc();
-        if (info->accel_state->exa == NULL) {
+        if (!info->accel_state->exa) {
             xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n");
             return FALSE;
         }
     }
 
-    if (info->allowColorTiling && !info->shadow_primary) {
-        if (info->ChipFamily >= CHIP_FAMILY_R600) {
-                if (info->allowColorTiling2D) {
-                        tiling_flags |= RADEON_TILING_MACRO;
-                } else {
-                        tiling_flags |= RADEON_TILING_MICRO;
-                }
-        } else
-            tiling_flags |= RADEON_TILING_MACRO;
-    }
-    pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
-    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
-    base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
-        if (info->ChipFamily >= CHIP_FAMILY_R600) {
-                if(!info->surf_man) {
-                        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                                   "failed to initialise surface manager\n");
-                        return FALSE;
-                }
-                memset(&surface, 0, sizeof(struct radeon_surface));
-                surface.npix_x = pScrn->virtualX;
-                surface.npix_y = pScrn->virtualY;
-                surface.npix_z = 1;
-                surface.blk_w = 1;
-                surface.blk_h = 1;
-                surface.blk_d = 1;
-                surface.array_size = 1;
-                surface.last_level = 0;
-                surface.bpe = cpp;
-                surface.nsamples = 1;
-                surface.flags = RADEON_SURF_SCANOUT;
-                /* we are requiring a recent enough libdrm version */
-                surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-                surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-                surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-                if (tiling_flags & RADEON_TILING_MICRO) {
-                        surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-                }
-                if (tiling_flags & RADEON_TILING_MACRO) {
-                        surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-                        surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-                }
-                if (radeon_surface_best(info->surf_man, &surface)) {
-                        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                                   "radeon_surface_best failed\n");
-                        return FALSE;
-                }
-                if (radeon_surface_init(info->surf_man, &surface)) {
-                        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                                   "radeon_surface_init failed\n");
-                        return FALSE;
-                }
-                pitch = surface.level[0].pitch_bytes;
-                screen_size = surface.bo_size;
-                base_align = surface.bo_alignment;
-                tiling_flags = 0;
-                switch (surface.level[0].mode) {
-                case RADEON_SURF_MODE_2D:
-                        tiling_flags |= RADEON_TILING_MACRO;
-                        tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
-                        tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
-                        tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
-                        if (surface.tile_split)
-                                tiling_flags |= eg_tile_split(surface.tile_split)
-                                                << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
-                        break;
-                case RADEON_SURF_MODE_1D:
-                        tiling_flags |= RADEON_TILING_MICRO;
-                        break;
-                default:
-                        break;
-                }
-                info->front_surface = surface;
-        }
     {
         int cursor_size;
         int c;
@@ -2764 +2700 @@
         cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
         for (c = 0; c < xf86_config->num_crtc; c++) {
             /* cursor objects */
-            if (info->cursor_bo[c] == NULL) {
+            if (!info->cursor_bo[c]) {
                 info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0,
                                                     cursor_size, 0,
                                                     RADEON_GEM_DOMAIN_VRAM, 0);
@@ -2782 +2718 @@
         }
     }
 
-    screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
+    if (!info->front_buffer) {
+        int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP;
+
+        if (info->allowColorTiling && !info->shadow_primary) {
+            if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D)
+                usage |= RADEON_CREATE_PIXMAP_TILING_MACRO;
+            else
+                usage |= RADEON_CREATE_PIXMAP_TILING_MICRO;
+        }
+
+        info->front_buffer = radeon_alloc_pixmap_bo(pScrn, pScrn->virtualX,
+                                                    pScrn->virtualY,
+                                                    pScrn->depth,
+                                                    usage,
+                                                    pScrn->bitsPerPixel,
+                                                    &pitch,
+                                                    &info->front_surface,
+                                                    &tiling_flags);
 
-    if (info->front_bo == NULL) {
-        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
-                                        base_align,
-                                        info->shadow_primary ?
-                                        RADEON_GEM_DOMAIN_GTT :
-                                        RADEON_GEM_DOMAIN_VRAM,
-                                        tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0);
         if (info->r600_shadow_fb == TRUE) {
-            if (radeon_bo_map(info->front_bo, 1)) {
+            if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) {
                 ErrorF("Failed to map cursor buffer memory\n");
             }
         }
+
+        if (!info->use_glamor) {
 #if X_BYTE_ORDER == X_BIG_ENDIAN
-        switch (cpp) {
-        case 4:
-            tiling_flags |= RADEON_TILING_SWAP_32BIT;
-            break;
-        case 2:
-            tiling_flags |= RADEON_TILING_SWAP_16BIT;
-            break;
-        }
-        if (info->ChipFamily < CHIP_FAMILY_R600 &&
-            info->r600_shadow_fb && tiling_flags)
-            tiling_flags |= RADEON_TILING_SURFACE;
+            switch (cpp) {
+            case 4:
+                tiling_flags |= RADEON_TILING_SWAP_32BIT;
+                break;
+            case 2:
+                tiling_flags |= RADEON_TILING_SWAP_16BIT;
+                break;
+            }
+            if (info->ChipFamily < CHIP_FAMILY_R600 &&
+                info->r600_shadow_fb && tiling_flags)
+                tiling_flags |= RADEON_TILING_SURFACE;
 #endif
-        if (tiling_flags)
-            radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
+            if (tiling_flags)
+                radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
+        }
     }
 
     pScrn->displayWidth = pitch / cpp;
 
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
-    radeon_kms_update_vram_limit(pScrn, screen_size);
+    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n",
+               pitch * pScrn->virtualY / 1024);
+    radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY);
     return TRUE;
 }
 
@@ -2828 +2778 @@
     int c;
 
     for (c = 0; c < xf86_config->num_crtc; c++) {
-        if (info->cursor_bo[c] != NULL) {
+        if (info->cursor_bo[c])
             new_fb_size += (64 * 4 * 64);
-        }
     }
 
     remain_size_bytes = info->vram_size - new_fb_size;

src/radeon_present.c

@@ -52 +52 @@
 
 struct radeon_present_vblank_event {
     uint64_t event_id;
-    Bool vblank_for_flip;
     Bool unflip;
 };
 
@@ -110 +109 @@
     if (r <= 0)
         return 0;
 
-    return drmHandleEvent(pRADEONEnt->fd, &drmmode->event_context) >= 0;
+    return radeon_drm_handle_event(pRADEONEnt->fd, &drmmode->event_context) >= 0;
 }
 
 /*
@@ -120 +119 @@
 radeon_present_vblank_handler(xf86CrtcPtr crtc, unsigned int msc,
                               uint64_t usec, void *data)
 {
-    drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
     struct radeon_present_vblank_event *event = data;
 
-    if (event->vblank_for_flip &&
-        drmmode_crtc->tear_free &&
-        drmmode_crtc->scanout_update_pending) {
-        if (drmmode_crtc->present_vblank_event_id != 0) {
-            xf86DrvMsg(crtc->scrn->scrnIndex, X_WARNING,
-                       "Need to handle previously deferred vblank event\n");
-            present_event_notify(drmmode_crtc->present_vblank_event_id,
-                                 drmmode_crtc->present_vblank_usec,
-                                 drmmode_crtc->present_vblank_msc);
-        }
-
-        drmmode_crtc->present_vblank_event_id = event->event_id;
-        drmmode_crtc->present_vblank_msc = msc;
-        drmmode_crtc->present_vblank_usec = usec;
-    } else
-        present_event_notify(event->event_id, usec, msc);
-
+    present_event_notify(event->event_id, usec, msc);
     free(event);
 }
 
@@ -162 +144 @@
 radeon_present_queue_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc)
 {
     xf86CrtcPtr xf86_crtc = crtc->devPrivate;
-    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
     ScreenPtr screen = crtc->pScreen;
     struct radeon_present_vblank_event *event;
     uintptr_t drm_queue_seq;
@@ -171 +152 @@
     if (!event)
         return BadAlloc;
     event->event_id = event_id;
-    event->vblank_for_flip = drmmode_crtc->present_flip_expected;
-    drmmode_crtc->present_flip_expected = FALSE;
 
     drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
                                            RADEON_DRM_QUEUE_CLIENT_DEFAULT,
@@ -272 +251 @@
               Bool sync_flip)
 {
     xf86CrtcPtr xf86_crtc = crtc->devPrivate;
-    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
     ScreenPtr screen = window->drawable.pScreen;
     ScrnInfoPtr scrn = xf86_crtc->scrn;
     xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
@@ -281 +259 @@
     int num_crtcs_on;
     int i;
 
-    drmmode_crtc->present_flip_expected = FALSE;
-
     if (!scrn->vtSema)
         return FALSE;
 
@@ -313 +289 @@
     if (num_crtcs_on == 0)
         return FALSE;
 
-    drmmode_crtc->present_flip_expected = TRUE;
     return TRUE;
 }
 
@@ -354 +329 @@
                    PixmapPtr pixmap, Bool sync_flip)
 {
     xf86CrtcPtr xf86_crtc = crtc->devPrivate;
-    drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
     ScreenPtr screen = crtc->pScreen;
     ScrnInfoPtr scrn = xf86_crtc->scrn;
     RADEONInfoPtr info = RADEONPTR(scrn);
@@ -362 +336 @@
     Bool ret = FALSE;
 
     if (!radeon_present_check_flip(crtc, screen->root, pixmap, sync_flip))
-        goto out;
+        return ret;
 
     event = calloc(1, sizeof(struct radeon_present_vblank_event));
     if (!event)
-        goto out;
+        return ret;
 
     event->event_id = event_id;
 
@@ -383 +357 @@
     else
         info->drmmode.present_flipping = TRUE;
 
- out:
-    drmmode_crtc->present_flip_expected = FALSE;
     return ret;
 }
 
@@ -404 +376 @@
         FLIP_ASYNC : FLIP_VSYNC;
     int i;
 
-    radeon_cs_flush_indirect(scrn);
-
     if (!radeon_present_check_unflip(scrn))
         goto modeset;
 
@@ -424 +394 @@
         return;
 
 modeset:
-    radeon_bo_wait(info->front_bo);
+    radeon_finish(scrn, info->front_buffer);
     for (i = 0; i < config->num_crtc; i++) {
         xf86CrtcPtr crtc = config->crtc[i];
         drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;

xf86-video-ati-18.0.1

@@ -278 +278 @@
 }
 #endif
 
-_X_EXPORT DriverRec RADEON =
+DriverRec RADEON =
 {
     RADEON_VERSION_CURRENT,
     RADEON_DRIVER_NAME,

src/radeon_textured_video.c

@@ -153 +153 @@
 static void
 RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 {
-    if (pPriv->video_memory != NULL) {
+    if (pPriv->video_memory) {
         radeon_bo_unref(pPriv->video_memory);
         pPriv->video_memory = NULL;
 
@@ -312 +312 @@
         RADEONFreeVideoMemory(pScrn, pPriv);
     }
 
-    if (pPriv->video_memory == NULL) {
+    if (!pPriv->video_memory) {
       Bool ret;
       ret = radeon_allocate_video_bo(pScrn,
                                      &pPriv->video_memory,
@@ -329 +329 @@
 
     /* Bicubic filter loading */
     if (pPriv->bicubic_enabled) {
-        if (info->bicubic_bo == NULL)
+        if (!info->bicubic_bo)
             pPriv->bicubic_enabled = FALSE;
     }
 
@@ -725 +725 @@
 {
     RADEONInfoPtr    info = RADEONPTR(pScrn);
 
-    if (info->bicubic_memory != NULL) {
+    if (info->bicubic_memory) {
         radeon_bo_unref(info->bicubic_memory);
         info->bicubic_memory = NULL;
     }
@@ -827 +827 @@
 
     adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
                    (sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
-    if (adapt == NULL)
+    if (!adapt)
         return NULL;
 
     xvBicubic         = MAKE_ATOM("XV_BICUBIC");

src/radeon_textured_videofuncs.c

@@ -63 +63 @@
     radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     if (pPriv->bicubic_enabled)
-        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo,
+                                          RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      RADEON_GEM_DOMAIN_VRAM);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret) {
@@ -433 +435 @@
     radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     if (pPriv->bicubic_enabled)
-        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo,
+                                          RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      RADEON_GEM_DOMAIN_VRAM);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret) {
@@ -958 +962 @@
     radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     if (pPriv->bicubic_enabled)
-        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo,
+                                          RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      RADEON_GEM_DOMAIN_VRAM);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret) {
@@ -2376 +2382 @@
     radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
     if (pPriv->bicubic_enabled)
-        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+        radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo,
+                                          RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
     
     driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0,
+                                      RADEON_GEM_DOMAIN_VRAM);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret) {

xf86-video-ati-18.0.1

@@ -144 +144 @@
 
     num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors);
     newAdaptors = malloc((num_adaptors + 2) * sizeof(*newAdaptors));
-    if (newAdaptors == NULL)
+    if (!newAdaptors)
         return;
 
     memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
@@ -152 +152 @@
 
     if (info->use_glamor) {
         texturedAdaptor = radeon_glamor_xv_init(pScreen, 16);
-        if (texturedAdaptor != NULL) {
+        if (texturedAdaptor) {
             adaptors[num_adaptors++] = texturedAdaptor;
             xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video (glamor)\n");
         } else
@@ -161 +161 @@
         || (info->directRenderingEnabled)
         ) {
         texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
-        if (texturedAdaptor != NULL) {
+        if (texturedAdaptor) {
             adaptors[num_adaptors++] = texturedAdaptor;
             xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
         } else