Ticket #11051: xf86-video-ati-upstream_patches-1.diff
File xf86-video-ati-upstream_patches-1.diff, 173.1 KB (added by , 6 years ago) |
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xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/ati.c xf86-video-ati-18.0.1/src/ati.c
old new 109 109 110 110 device_iter = pci_slot_match_iterator_create(NULL); 111 111 112 while ((device = pci_device_next(device_iter)) != NULL) {112 while ((device = pci_device_next(device_iter))) { 113 113 if (xf86IsPrimaryPci(device)) 114 114 break; 115 115 } … … 128 128 129 129 device_iter = pci_slot_match_iterator_create(NULL); 130 130 131 while ((device = pci_device_next(device_iter)) != NULL) {131 while ((device = pci_device_next(device_iter))) { 132 132 if (device->vendor_id == PCI_VENDOR_ATI) { 133 133 if (count == index) 134 134 return device; -
src/drmmode_display.c
diff -Naur xf86-video-ati-18.0.1.orig/src/drmmode_display.c xf86-video-ati-18.0.1/src/drmmode_display.c
old new 100 100 } 101 101 102 102 103 /* Wait for the boolean condition to be FALSE */104 #define drmmode_crtc_wait_pending_event(drmmode_crtc, fd, condition) \105 do {} while ((condition) && \106 drmHandleEvent(fd, &drmmode_crtc->drmmode->event_context) \107 > 0);108 109 110 103 static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn, 111 104 int width, int height, 112 105 int depth, int bpp, 113 106 int pitch, 114 struct radeon_b o *bo, struct radeon_surface *psurf)107 struct radeon_buffer *bo) 115 108 { 116 109 RADEONInfoPtr info = RADEONPTR(pScrn); 117 110 ScreenPtr pScreen = pScrn->pScreen; 118 111 PixmapPtr pixmap; 119 struct radeon_surface *surface;120 uint32_t tiling;121 112 122 113 pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth, 123 114 RADEON_CREATE_PIXMAP_SCANOUT); … … 135 126 if (!radeon_set_pixmap_bo(pixmap, bo)) 136 127 goto fail; 137 128 138 if (info->ChipFamily >= CHIP_FAMILY_R600) { 139 surface = radeon_get_pixmap_surface(pixmap); 140 if (surface && psurf) 141 *surface = *psurf; 142 else if (surface) { 143 memset(surface, 0, sizeof(struct radeon_surface)); 144 surface->npix_x = width; 145 surface->npix_y = height; 146 surface->npix_z = 1; 147 surface->blk_w = 1; 148 surface->blk_h = 1; 149 surface->blk_d = 1; 150 surface->array_size = 1; 151 surface->last_level = 0; 152 surface->bpe = bpp / 8; 153 surface->nsamples = 1; 154 surface->flags = RADEON_SURF_SCANOUT; 155 /* we are requiring a recent enough libdrm version */ 156 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 157 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 158 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 159 tiling = radeon_get_pixmap_tiling_flags(pixmap); 160 if (tiling & RADEON_TILING_MICRO) { 161 surface->flags = RADEON_SURF_CLR(surface->flags, MODE); 162 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 163 } 164 if (tiling & RADEON_TILING_MACRO) { 165 surface->flags = RADEON_SURF_CLR(surface->flags, MODE); 166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 167 } 168 if (radeon_surface_best(info->surf_man, surface)) { 169 goto fail; 170 } 171 if (radeon_surface_init(info->surf_man, surface)) { 172 goto fail; 173 } 174 } 129 if (info->surf_man && !info->use_glamor) { 130 struct radeon_surface *surface = radeon_get_pixmap_surface(pixmap); 131 132 if (!radeon_surface_initialize(info, surface, width, height, bpp / 8, 133 radeon_get_pixmap_tiling_flags(pixmap), 0)) 134 goto fail; 175 135 } 176 136 177 137 if (!info->use_glamor || 178 radeon_glamor_create_textured_pixmap(pixmap, 179 radeon_get_pixmap_private(pixmap))) 138 radeon_glamor_create_textured_pixmap(pixmap, bo)) 180 139 return pixmap; 181 140 182 141 fail: … … 340 299 if (drmmode_crtc->dpms_mode == DPMSModeOn && mode != DPMSModeOn) { 341 300 uint32_t seq; 342 301 343 drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd, 344 drmmode_crtc->flip_pending); 302 radeon_drm_wait_pending_flip(crtc); 345 303 346 304 /* 347 305 * On->Off transition: record the last vblank time, … … 366 324 nominal_frame_rate /= pix_in_frame; 367 325 drmmode_crtc->dpms_last_fps = nominal_frame_rate; 368 326 } 327 328 drmmode_crtc->dpms_mode = mode; 329 radeon_drm_queue_handle_deferred(crtc); 369 330 } else if (drmmode_crtc->dpms_mode != DPMSModeOn && mode == DPMSModeOn) { 370 331 /* 371 332 * Off->On transition: calculate and accumulate the … … 383 344 drmmode_crtc->interpolated_vblanks += delta_seq; 384 345 385 346 } 347 348 drmmode_crtc->dpms_mode = DPMSModeOn; 386 349 } 387 drmmode_crtc->dpms_mode = mode;388 350 } 389 351 390 352 static void … … 395 357 396 358 /* Disable unused CRTCs */ 397 359 if (!crtc->enabled || mode != DPMSModeOn) { 398 drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd, 399 drmmode_crtc->flip_pending); 360 drmmode_do_crtc_dpms(crtc, DPMSModeOff); 400 361 drmModeSetCrtc(pRADEONEnt->fd, drmmode_crtc->mode_crtc->crtc_id, 401 362 0, 0, 0, NULL, 0, NULL); 402 363 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL); … … 412 373 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 413 374 RADEONInfoPtr info = RADEONPTR(pScrn); 414 375 PixmapPtr pixmap = info->fbcon_pixmap; 415 struct radeon_b o*bo;376 struct radeon_buffer *bo; 416 377 drmModeFBPtr fbcon; 417 378 struct drm_gem_flink flink; 418 379 … … 420 381 return pixmap; 421 382 422 383 fbcon = drmModeGetFB(pRADEONEnt->fd, fbcon_id); 423 if ( fbcon == NULL)384 if (!fbcon) 424 385 return NULL; 425 386 426 387 if (fbcon->depth != pScrn->depth || … … 435 396 goto out_free_fb; 436 397 } 437 398 438 bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);439 if ( bo == NULL) {399 bo = calloc(1, sizeof(struct radeon_buffer)); 400 if (!bo) { 440 401 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 441 "Couldn't allocate bo for fbcon handle\n"); 402 "Couldn't allocate BO for fbcon handle\n"); 403 goto out_free_fb; 404 } 405 bo->ref_count = 1; 406 407 bo->bo.radeon = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0); 408 if (!bo) { 409 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 410 "Couldn't open BO for fbcon handle\n"); 442 411 goto out_free_fb; 443 412 } 444 413 445 414 pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height, 446 415 fbcon->depth, fbcon->bpp, fbcon->pitch, 447 bo , NULL);416 bo); 448 417 info->fbcon_pixmap = pixmap; 449 radeon_b o_unref(bo);418 radeon_buffer_unref(&bo); 450 419 out_free_fb: 451 420 drmModeFreeFB(fbcon); 452 421 return pixmap; … … 460 429 /* XXX: The current GPUVM support in the kernel doesn't allow removing 461 430 * the virtual address range for this BO, so we need to keep around 462 431 * the pixmap to avoid breaking glamor with GPUVM 432 * 433 * Similarly, need to keep around the pixmap with current glamor, to 434 * avoid issues due to a GEM handle lifetime conflict between us and 435 * Mesa 463 436 */ 464 if (info->use_glamor && info->ChipFamily >= CHIP_FAMILY_CAYMAN) 437 if (info->use_glamor && 438 (info->ChipFamily >= CHIP_FAMILY_CAYMAN || 439 xorgGetVersion() >= XORG_VERSION_NUMERIC(1,19,99,1,0))) 465 440 return; 466 441 467 442 if (info->fbcon_pixmap) … … 529 504 scanout->pixmap = NULL; 530 505 } 531 506 532 if (scanout->bo) { 533 radeon_bo_unmap(scanout->bo); 534 radeon_bo_unref(scanout->bo); 535 scanout->bo = NULL; 536 } 507 radeon_buffer_unref(&scanout->bo); 537 508 } 538 509 539 510 void … … 581 552 width, height, 582 553 pScrn->depth, 583 554 pScrn->bitsPerPixel, 584 pitch, scanout->bo , NULL);555 pitch, scanout->bo); 585 556 if (!scanout->pixmap) { 586 557 ErrorF("failed to create CRTC scanout pixmap\n"); 587 558 goto error; … … 693 664 Bool ret; 694 665 695 666 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,15,99,903,0) 696 if (crtc->transformPresent || crtc->rotation != RR_Rotate_0) 697 crtc->driverIsPerformingTransform = XF86DriverTransformOutput; 698 else 699 crtc->driverIsPerformingTransform = XF86DriverTransformNone; 667 crtc->driverIsPerformingTransform = XF86DriverTransformOutput; 700 668 #else 701 669 crtc->driverIsPerformingTransform = !crtc->transformPresent && 702 crtc->rotation != RR_Rotate_0 &&703 670 (crtc->rotation & 0xf) == RR_Rotate_0; 704 671 #endif 705 672 … … 759 726 gc, 0, 0, mode->HDisplay, mode->VDisplay, 760 727 0, 0); 761 728 FreeScratchGC(gc); 762 radeon_cs_flush_indirect(scrn); 763 radeon_bo_wait(drmmode_crtc->scanout[0].bo); 729 radeon_finish(scrn, drmmode_crtc->scanout[0].bo); 764 730 } 765 731 } 766 732 … … 790 756 if (drmmode_crtc->scanout[scanout_id].pixmap && 791 757 (!drmmode_crtc->tear_free || 792 758 drmmode_crtc->scanout[scanout_id ^ 1].pixmap)) { 793 RegionPtr region;794 BoxPtr box;759 BoxRec extents = { .x1 = 0, .y1 = 0, 760 .x2 = scrn->virtualX, .y2 = scrn->virtualY }; 795 761 796 762 if (!drmmode_crtc->scanout_damage) { 797 763 drmmode_crtc->scanout_damage = … … 803 769 drmmode_crtc->scanout_damage); 804 770 } 805 771 806 region = DamageRegion(drmmode_crtc->scanout_damage);807 RegionUninit(region);808 region->data = NULL;809 box = RegionExtents(region);810 box->x1 = 0;811 box->y1 = 0;812 box->x2 = max(box->x2, scrn->virtualX);813 box->y2 = max(box->y2, scrn->virtualY);814 815 772 *fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 816 773 *x = *y = 0; 817 774 818 775 radeon_scanout_do_update(crtc, scanout_id, 819 776 screen->GetWindowPixmap(screen->root), 820 *box); 821 radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo); 777 extents); 778 RegionEmpty(DamageRegion(drmmode_crtc->scanout_damage)); 779 radeon_finish(scrn, drmmode_crtc->scanout[scanout_id].bo); 822 780 } 823 781 } 824 782 … … 922 880 drmmode_crtc_update_tear_free(crtc); 923 881 if (drmmode_crtc->tear_free) 924 882 scanout_id = drmmode_crtc->scanout_id; 925 926 drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red, crtc->gamma_green, 927 crtc->gamma_blue, crtc->gamma_size); 883 else 884 drmmode_crtc->scanout_id = 0; 928 885 929 886 if (drmmode_crtc->prime_scanout_pixmap) { 930 887 drmmode_crtc_prime_scanout_update(crtc, mode, scanout_id, … … 947 904 fb = radeon_fb_create(pScrn, pRADEONEnt->fd, 948 905 pScrn->virtualX, pScrn->virtualY, 949 906 pScrn->displayWidth * info->pixel_bytes, 950 info->front_b o->handle);907 info->front_buffer->bo.radeon->handle); 951 908 /* Prevent refcnt of ad-hoc FBs from reaching 2 */ 952 909 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL); 953 910 drmmode_crtc->fb = fb; … … 957 914 goto done; 958 915 } 959 916 960 drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd, 961 drmmode_crtc->flip_pending); 917 radeon_drm_wait_pending_flip(crtc); 962 918 963 919 if (!drmmode_set_mode(crtc, fb, mode, x, y)) 964 920 goto done; … … 1010 966 1011 967 if (drmmode_crtc->scanout[scanout_id].pixmap && 1012 968 fb != radeon_pixmap_get_fb(drmmode_crtc-> 1013 scanout[scanout_id].pixmap)) 969 scanout[scanout_id].pixmap)) { 970 radeon_drm_abort_entry(drmmode_crtc->scanout_update_pending); 971 drmmode_crtc->scanout_update_pending = 0; 1014 972 drmmode_crtc_scanout_free(drmmode_crtc); 1015 else if (!drmmode_crtc->tear_free) {973 } else if (!drmmode_crtc->tear_free) { 1016 974 drmmode_crtc_scanout_destroy(drmmode, 1017 975 &drmmode_crtc->scanout[1]); 1018 976 } 1019 977 } 1020 978 979 radeon_drm_queue_handle_deferred(crtc); 1021 980 return ret; 1022 981 } 1023 982 … … 1398 1357 RADEONInfoPtr info = RADEONPTR(pScrn); 1399 1358 1400 1359 crtc = xf86CrtcCreate(pScrn, &info->drmmode_crtc_funcs); 1401 if ( crtc == NULL)1360 if (!crtc) 1402 1361 return 0; 1403 1362 1404 1363 drmmode_crtc = xnfcalloc(sizeof(drmmode_crtc_private_rec), 1); … … 1680 1639 RADEONEntPtr pRADEONEnt = RADEONEntPriv(output->scrn); 1681 1640 drmModePropertyPtr drmmode_prop, tearfree_prop; 1682 1641 int i, j, err; 1642 Atom name; 1643 1644 /* Create CONNECTOR_ID property */ 1645 name = MakeAtom("CONNECTOR_ID", 12, TRUE); 1646 if (name != BAD_RESOURCE) { 1647 INT32 value = mode_output->connector_id; 1648 1649 err = RRConfigureOutputProperty(output->randr_output, name, 1650 FALSE, FALSE, TRUE, 1, &value); 1651 if (err != Success) { 1652 xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, 1653 "RRConfigureOutputProperty error, %d\n", err); 1654 } 1655 1656 err = RRChangeOutputProperty(output->randr_output, name, 1657 XA_INTEGER, 32, PropModeReplace, 1, 1658 &value, FALSE, FALSE); 1659 if (err != Success) { 1660 xf86DrvMsg(output->scrn->scrnIndex, X_ERROR, 1661 "RRChangeOutputProperty error, %d\n", err); 1662 } 1663 } 1683 1664 1684 1665 drmmode_output->props = calloc(mode_output->count_props + 1, sizeof(drmmode_prop_rec)); 1685 1666 if (!drmmode_output->props) … … 1701 1682 /* Userspace-only property for TearFree */ 1702 1683 tearfree_prop = calloc(1, sizeof(*tearfree_prop)); 1703 1684 tearfree_prop->flags = DRM_MODE_PROP_ENUM; 1704 str ncpy(tearfree_prop->name, "TearFree", 8);1685 strcpy(tearfree_prop->name, "TearFree"); 1705 1686 tearfree_prop->count_enums = 3; 1706 1687 tearfree_prop->enums = calloc(tearfree_prop->count_enums, 1707 1688 sizeof(*tearfree_prop->enums)); 1708 str ncpy(tearfree_prop->enums[0].name, "off", 3);1709 str ncpy(tearfree_prop->enums[1].name, "on", 2);1689 strcpy(tearfree_prop->enums[0].name, "off"); 1690 strcpy(tearfree_prop->enums[1].name, "on"); 1710 1691 tearfree_prop->enums[1].value = 1; 1711 str ncpy(tearfree_prop->enums[2].name, "auto", 4);1692 strcpy(tearfree_prop->enums[2].name, "auto"); 1712 1693 tearfree_prop->enums[2].value = 2; 1713 1694 drmmode_output->props[j].mode_prop = tearfree_prop; 1714 1695 drmmode_output->props[j].value = info->tear_free; … … 1776 1757 } 1777 1758 } 1778 1759 1760 static void 1761 drmmode_output_set_tear_free(RADEONEntPtr pRADEONEnt, 1762 drmmode_output_private_ptr drmmode_output, 1763 xf86CrtcPtr crtc, int tear_free) 1764 { 1765 if (drmmode_output->tear_free == tear_free) 1766 return; 1767 1768 drmmode_output->tear_free = tear_free; 1769 1770 if (crtc) { 1771 drmmode_set_mode_major(crtc, &crtc->mode, crtc->rotation, 1772 crtc->x, crtc->y); 1773 } 1774 } 1775 1779 1776 static Bool 1780 1777 drmmode_output_set_property(xf86OutputPtr output, Atom property, 1781 1778 RRPropertyValuePtr value) … … 1816 1813 for (j = 0; j < p->mode_prop->count_enums; j++) { 1817 1814 if (!strcmp(p->mode_prop->enums[j].name, name)) { 1818 1815 if (i == (drmmode_output->num_props - 1)) { 1819 if (drmmode_output->tear_free != j) { 1820 xf86CrtcPtr crtc = output->crtc; 1821 1822 drmmode_output->tear_free = j; 1823 if (crtc) { 1824 drmmode_set_mode_major(crtc, &crtc->mode, 1825 crtc->rotation, 1826 crtc->x, crtc->y); 1827 } 1828 } 1816 drmmode_output_set_tear_free(pRADEONEnt, drmmode_output, 1817 output->crtc, j); 1829 1818 } else { 1830 1819 drmModeConnectorSetProperty(pRADEONEnt->fd, 1831 1820 drmmode_output->output_id, … … 1853 1842 .create_resources = drmmode_output_create_resources, 1854 1843 .set_property = drmmode_output_set_property, 1855 1844 .get_property = drmmode_output_get_property, 1856 #if 01857 1858 .save = drmmode_crt_save,1859 .restore = drmmode_crt_restore,1860 .mode_fixup = drmmode_crt_mode_fixup,1861 .prepare = drmmode_output_prepare,1862 .mode_set = drmmode_crt_mode_set,1863 .commit = drmmode_output_commit,1864 #endif1865 1845 .detect = drmmode_output_detect, 1866 1846 .mode_valid = drmmode_output_mode_valid, 1867 1847 … … 2005 1985 drmModeEncoderPtr *kencoders = NULL; 2006 1986 drmmode_output_private_ptr drmmode_output; 2007 1987 drmModePropertyBlobPtr path_blob = NULL; 1988 #if XF86_CRTC_VERSION >= 8 1989 Bool nonDesktop = FALSE; 1990 #endif 2008 1991 char name[32]; 2009 1992 int i; 2010 1993 const char *s; … … 2015 1998 2016 1999 path_blob = koutput_get_prop_blob(pRADEONEnt->fd, koutput, "PATH"); 2017 2000 2001 #if XF86_CRTC_VERSION >= 8 2002 i = koutput_get_prop_idx(pRADEONEnt->fd, koutput, DRM_MODE_PROP_RANGE, 2003 "non-desktop"); 2004 if (i >= 0) 2005 nonDesktop = koutput->prop_values[i] != 0; 2006 #endif 2007 2018 2008 kencoders = calloc(sizeof(drmModeEncoderPtr), koutput->count_encoders); 2019 2009 if (!kencoders) { 2020 2010 goto out_free_encoders; … … 2044 2034 drmmode_output = output->driver_private; 2045 2035 drmmode_output->output_id = mode_res->connectors[num]; 2046 2036 drmmode_output->mode_output = koutput; 2037 #if XF86_CRTC_VERSION >= 8 2038 output->non_desktop = nonDesktop; 2039 #endif 2047 2040 for (i = 0; i < koutput->count_encoders; i++) 2048 2041 drmModeFreeEncoder(kencoders[i]); 2049 2042 free(kencoders); … … 2085 2078 output->interlaceAllowed = TRUE; 2086 2079 output->doubleScanAllowed = TRUE; 2087 2080 output->driver_private = drmmode_output; 2081 #if XF86_CRTC_VERSION >= 8 2082 output->non_desktop = nonDesktop; 2083 #endif 2088 2084 2089 2085 output->possible_crtcs = 0xffffffff; 2090 2086 for (i = 0; i < koutput->count_encoders; i++) { … … 2266 2262 { 2267 2263 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 2268 2264 RADEONInfoPtr info = RADEONPTR(scrn); 2269 struct radeon_b o*old_front = NULL;2265 struct radeon_buffer *old_front = NULL; 2270 2266 ScreenPtr screen = xf86ScrnToScreen(scrn); 2271 2267 int i, pitch, old_width, old_height, old_pitch; 2272 int aligned_height; 2273 uint32_t screen_size; 2268 int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP; 2274 2269 int cpp = info->pixel_bytes; 2275 struct radeon_bo *front_bo; 2276 struct radeon_surface surface; 2277 struct radeon_surface *psurface; 2278 uint32_t tiling_flags = 0, base_align; 2270 uint32_t tiling_flags; 2279 2271 PixmapPtr ppix = screen->GetScreenPixmap(screen); 2280 2272 void *fb_shadow; 2281 2273 2282 2274 if (scrn->virtualX == width && scrn->virtualY == height) 2283 2275 return TRUE; 2284 2276 2285 front_bo = info->front_bo; 2286 radeon_cs_flush_indirect(scrn); 2287 2288 if (front_bo) 2289 radeon_bo_wait(front_bo); 2290 2291 if (info->allowColorTiling && !info->shadow_primary) { 2292 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2293 if (info->allowColorTiling2D) { 2294 tiling_flags |= RADEON_TILING_MACRO; 2295 } else { 2296 tiling_flags |= RADEON_TILING_MICRO; 2297 } 2298 } else 2299 tiling_flags |= RADEON_TILING_MACRO; 2277 if (width > xf86_config->maxWidth || height > xf86_config->maxHeight) { 2278 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 2279 "Xorg tried resizing screen to %dx%d, but maximum " 2280 "supported is %dx%d\n", width, height, 2281 xf86_config->maxWidth, xf86_config->maxHeight); 2282 return FALSE; 2300 2283 } 2301 2284 2302 pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp; 2303 aligned_height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags)); 2304 screen_size = RADEON_ALIGN(pitch * aligned_height, RADEON_GPU_PAGE_SIZE); 2305 base_align = 4096; 2306 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2307 memset(&surface, 0, sizeof(struct radeon_surface)); 2308 surface.npix_x = width; 2309 surface.npix_y = height; 2310 surface.npix_z = 1; 2311 surface.blk_w = 1; 2312 surface.blk_h = 1; 2313 surface.blk_d = 1; 2314 surface.array_size = 1; 2315 surface.last_level = 0; 2316 surface.bpe = cpp; 2317 surface.nsamples = 1; 2318 surface.flags = RADEON_SURF_SCANOUT; 2319 /* we are requiring a recent enough libdrm version */ 2320 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 2321 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 2322 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 2323 if (tiling_flags & RADEON_TILING_MICRO) { 2324 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2325 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 2326 } 2327 if (tiling_flags & RADEON_TILING_MACRO) { 2328 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 2329 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 2330 } 2331 if (radeon_surface_best(info->surf_man, &surface)) { 2332 return FALSE; 2333 } 2334 if (radeon_surface_init(info->surf_man, &surface)) { 2335 return FALSE; 2336 } 2337 screen_size = surface.bo_size; 2338 base_align = surface.bo_alignment; 2339 pitch = surface.level[0].pitch_bytes; 2340 tiling_flags = 0; 2341 switch (surface.level[0].mode) { 2342 case RADEON_SURF_MODE_2D: 2343 tiling_flags |= RADEON_TILING_MACRO; 2344 tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 2345 tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 2346 tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 2347 if (surface.tile_split) 2348 tiling_flags |= eg_tile_split(surface.tile_split) 2349 << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 2350 break; 2351 case RADEON_SURF_MODE_1D: 2352 tiling_flags |= RADEON_TILING_MICRO; 2353 break; 2354 default: 2355 break; 2356 } 2357 info->front_surface = surface; 2285 if (info->allowColorTiling && !info->shadow_primary) { 2286 if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D) 2287 usage |= RADEON_CREATE_PIXMAP_TILING_MACRO; 2288 else 2289 usage |= RADEON_CREATE_PIXMAP_TILING_MICRO; 2358 2290 } 2359 2291 2360 xf86DrvMsg(scrn->scrnIndex, X_INFO, 2361 "Allocate new frame buffer %dx%d stride %d\n", 2362 width, height, pitch / cpp); 2292 xf86DrvMsg(scrn->scrnIndex, X_INFO, "Allocate new frame buffer %dx%d\n", 2293 width, height); 2363 2294 2364 2295 old_width = scrn->virtualX; 2365 2296 old_height = scrn->virtualY; 2366 2297 old_pitch = scrn->displayWidth; 2367 old_front = info->front_b o;2298 old_front = info->front_buffer; 2368 2299 2369 2300 scrn->virtualX = width; 2370 2301 scrn->virtualY = height; 2371 scrn->displayWidth = pitch / cpp;2372 2302 2373 info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align, 2374 info->shadow_primary ? 2375 RADEON_GEM_DOMAIN_GTT : 2376 RADEON_GEM_DOMAIN_VRAM, 2377 tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0); 2378 if (!info->front_bo) 2303 info->front_buffer = radeon_alloc_pixmap_bo(scrn, scrn->virtualX, 2304 scrn->virtualY, scrn->depth, 2305 usage, scrn->bitsPerPixel, 2306 &pitch, 2307 &info->front_surface, 2308 &tiling_flags); 2309 if (!info->front_buffer) 2379 2310 goto fail; 2380 2311 2312 scrn->displayWidth = pitch / cpp; 2313 2314 if (!info->use_glamor) { 2381 2315 #if X_BYTE_ORDER == X_BIG_ENDIAN 2382 switch (cpp) {2383 case 4:2384 2385 2386 case 2:2387 2388 2389 }2390 if (info->ChipFamily < CHIP_FAMILY_R600 &&2391 info->r600_shadow_fb && tiling_flags)2392 2316 switch (cpp) { 2317 case 4: 2318 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2319 break; 2320 case 2: 2321 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2322 break; 2323 } 2324 if (info->ChipFamily < CHIP_FAMILY_R600 && 2325 info->r600_shadow_fb && tiling_flags) 2326 tiling_flags |= RADEON_TILING_SURFACE; 2393 2327 #endif 2394 if (tiling_flags) 2395 radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); 2328 if (tiling_flags) 2329 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch); 2330 } 2396 2331 2397 2332 if (!info->r600_shadow_fb) { 2398 psurface = radeon_get_pixmap_surface(ppix);2399 *psurface= info->front_surface;2333 if (info->surf_man && !info->use_glamor) 2334 *radeon_get_pixmap_surface(ppix) = info->front_surface; 2400 2335 screen->ModifyPixmapHeader(ppix, 2401 2336 width, height, -1, -1, pitch, NULL); 2402 2337 } else { 2403 if (radeon_bo_map(info->front_b o, 1))2338 if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) 2404 2339 goto fail; 2405 fb_shadow = calloc(1, screen_size);2406 if ( fb_shadow == NULL)2340 fb_shadow = calloc(1, pitch * scrn->virtualY); 2341 if (!fb_shadow) 2407 2342 goto fail; 2408 2343 free(info->fb_shadow); 2409 2344 info->fb_shadow = fb_shadow; … … 2416 2351 radeon_glamor_create_screen_resources(scrn->pScreen); 2417 2352 2418 2353 if (!info->r600_shadow_fb) { 2419 if (!radeon_set_pixmap_bo(ppix, info->front_b o))2354 if (!radeon_set_pixmap_bo(ppix, info->front_buffer)) 2420 2355 goto fail; 2421 2356 } 2422 2357 2423 2358 radeon_pixmap_clear(ppix); 2424 radeon_cs_flush_indirect(scrn); 2425 radeon_bo_wait(info->front_bo); 2359 radeon_finish(scrn, info->front_buffer); 2426 2360 2427 2361 for (i = 0; i < xf86_config->num_crtc; i++) { 2428 2362 xf86CrtcPtr crtc = xf86_config->crtc[i]; … … 2434 2368 crtc->rotation, crtc->x, crtc->y); 2435 2369 } 2436 2370 2437 if (old_front) 2438 radeon_bo_unref(old_front); 2371 radeon_buffer_unref(&old_front); 2439 2372 2440 radeon_kms_update_vram_limit(scrn, screen_size);2373 radeon_kms_update_vram_limit(scrn, pitch * scrn->virtualY); 2441 2374 return TRUE; 2442 2375 2443 2376 fail: 2444 if (info->front_bo) 2445 radeon_bo_unref(info->front_bo); 2446 info->front_bo = old_front; 2377 radeon_buffer_unref(&info->front_buffer); 2378 info->front_buffer = old_front; 2447 2379 scrn->virtualX = old_width; 2448 2380 scrn->virtualY = old_height; 2449 2381 scrn->displayWidth = old_pitch; … … 2451 2383 return FALSE; 2452 2384 } 2453 2385 2386 static void 2387 drmmode_validate_leases(ScrnInfoPtr scrn) 2388 { 2389 #ifdef XF86_LEASE_VERSION 2390 ScreenPtr screen = scrn->pScreen; 2391 rrScrPrivPtr scr_priv = rrGetScrPriv(screen); 2392 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2393 drmModeLesseeListPtr lessees; 2394 RRLeasePtr lease, next; 2395 int l; 2396 2397 /* We can't talk to the kernel about leases when VT switched */ 2398 if (!scrn->vtSema) 2399 return; 2400 2401 lessees = drmModeListLessees(pRADEONEnt->fd); 2402 if (!lessees) 2403 return; 2404 2405 xorg_list_for_each_entry_safe(lease, next, &scr_priv->leases, list) { 2406 drmmode_lease_private_ptr lease_private = lease->devPrivate; 2407 2408 for (l = 0; l < lessees->count; l++) { 2409 if (lessees->lessees[l] == lease_private->lessee_id) 2410 break; 2411 } 2412 2413 /* check to see if the lease has gone away */ 2414 if (l == lessees->count) { 2415 free(lease_private); 2416 lease->devPrivate = NULL; 2417 xf86CrtcLeaseTerminated(lease); 2418 } 2419 } 2420 2421 free(lessees); 2422 #endif 2423 } 2424 2425 #ifdef XF86_LEASE_VERSION 2426 2427 static int 2428 drmmode_create_lease(RRLeasePtr lease, int *fd) 2429 { 2430 ScreenPtr screen = lease->screen; 2431 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 2432 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2433 drmmode_lease_private_ptr lease_private; 2434 int noutput = lease->numOutputs; 2435 int ncrtc = lease->numCrtcs; 2436 uint32_t *objects; 2437 size_t nobjects; 2438 int lease_fd; 2439 int c, o; 2440 int i; 2441 2442 nobjects = ncrtc + noutput; 2443 if (nobjects == 0 || nobjects > (SIZE_MAX / 4) || 2444 ncrtc > (SIZE_MAX - noutput)) 2445 return BadValue; 2446 2447 lease_private = calloc(1, sizeof (drmmode_lease_private_rec)); 2448 if (!lease_private) 2449 return BadAlloc; 2450 2451 objects = malloc(nobjects * 4); 2452 if (!objects) { 2453 free(lease_private); 2454 return BadAlloc; 2455 } 2456 2457 i = 0; 2458 2459 /* Add CRTC ids */ 2460 for (c = 0; c < ncrtc; c++) { 2461 xf86CrtcPtr crtc = lease->crtcs[c]->devPrivate; 2462 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 2463 2464 objects[i++] = drmmode_crtc->mode_crtc->crtc_id; 2465 } 2466 2467 /* Add connector ids */ 2468 for (o = 0; o < noutput; o++) { 2469 xf86OutputPtr output = lease->outputs[o]->devPrivate; 2470 drmmode_output_private_ptr drmmode_output = output->driver_private; 2471 2472 objects[i++] = drmmode_output->mode_output->connector_id; 2473 } 2474 2475 /* call kernel to create lease */ 2476 assert (i == nobjects); 2477 2478 lease_fd = drmModeCreateLease(pRADEONEnt->fd, objects, nobjects, 0, 2479 &lease_private->lessee_id); 2480 2481 free(objects); 2482 2483 if (lease_fd < 0) { 2484 free(lease_private); 2485 return BadMatch; 2486 } 2487 2488 lease->devPrivate = lease_private; 2489 2490 xf86CrtcLeaseStarted(lease); 2491 2492 *fd = lease_fd; 2493 return Success; 2494 } 2495 2496 static void 2497 drmmode_terminate_lease(RRLeasePtr lease) 2498 { 2499 drmmode_lease_private_ptr lease_private = lease->devPrivate; 2500 ScreenPtr screen = lease->screen; 2501 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 2502 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2503 2504 if (drmModeRevokeLease(pRADEONEnt->fd, lease_private->lessee_id) == 0) { 2505 free(lease_private); 2506 lease->devPrivate = NULL; 2507 xf86CrtcLeaseTerminated(lease); 2508 } 2509 } 2510 2511 #endif // XF86_LEASE_VERSION 2512 2454 2513 static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = { 2455 drmmode_xf86crtc_resize 2514 .resize = drmmode_xf86crtc_resize, 2515 #ifdef XF86_LEASE_VERSION 2516 .create_lease = drmmode_create_lease, 2517 .terminate_lease = drmmode_terminate_lease 2518 #endif 2456 2519 }; 2457 2520 2458 2521 static void … … 2461 2524 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 2462 2525 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 2463 2526 drmmode_flipdata_ptr flipdata = event_data; 2527 int crtc_id = drmmode_get_crtc_id(crtc); 2528 struct drmmode_fb **fb = &flipdata->fb[crtc_id]; 2529 2530 if (drmmode_crtc->flip_pending == *fb) { 2531 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 2532 NULL); 2533 } 2534 drmmode_fb_reference(pRADEONEnt->fd, fb, NULL); 2464 2535 2465 2536 if (--flipdata->flip_count == 0) { 2466 2537 if (!flipdata->fe_crtc) 2467 2538 flipdata->fe_crtc = crtc; 2468 2539 flipdata->abort(flipdata->fe_crtc, flipdata->event_data); 2469 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);2470 2540 free(flipdata); 2471 2541 } 2472 2473 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,2474 NULL);2475 2542 } 2476 2543 2477 2544 static void … … 2480 2547 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 2481 2548 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 2482 2549 drmmode_flipdata_ptr flipdata = event_data; 2550 int crtc_id = drmmode_get_crtc_id(crtc); 2551 struct drmmode_fb **fb = &flipdata->fb[crtc_id]; 2483 2552 2484 2553 /* Is this the event whose info shall be delivered to higher level? */ 2485 2554 if (crtc == flipdata->fe_crtc) { … … 2488 2557 flipdata->fe_usec = usec; 2489 2558 } 2490 2559 2491 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, 2492 flipdata->fb); 2493 if (drmmode_crtc->tear_free || 2494 drmmode_crtc->flip_pending == flipdata->fb) { 2560 if (drmmode_crtc->flip_pending == *fb) { 2495 2561 drmmode_fb_reference(pRADEONEnt->fd, 2496 2562 &drmmode_crtc->flip_pending, NULL); 2497 2563 } 2564 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, *fb); 2565 drmmode_fb_reference(pRADEONEnt->fd, fb, NULL); 2498 2566 2499 2567 if (--flipdata->flip_count == 0) { 2500 2568 /* Deliver MSC & UST from reference/current CRTC to flip event … … 2506 2574 else 2507 2575 flipdata->handler(crtc, frame, usec, flipdata->event_data); 2508 2576 2509 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);2510 2577 free(flipdata); 2511 2578 } 2512 2579 } … … 2520 2587 drm_wakeup_handler(pointer data, int err, pointer p) 2521 2588 #endif 2522 2589 { 2523 ScrnInfoPtr scrn = data; 2524 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2525 RADEONInfoPtr info = RADEONPTR(scrn); 2590 drmmode_ptr drmmode = data; 2591 RADEONEntPtr pRADEONEnt = RADEONEntPriv(drmmode->scrn); 2526 2592 2527 2593 #if !HAVE_NOTIFY_FD 2528 2594 fd_set *read_mask = p; … … 2530 2596 if (err >= 0 && FD_ISSET(pRADEONEnt->fd, read_mask)) 2531 2597 #endif 2532 2598 { 2533 drmHandleEvent(pRADEONEnt->fd, &info->drmmode.event_context);2599 radeon_drm_handle_event(pRADEONEnt->fd, &drmmode->event_context); 2534 2600 } 2535 2601 } 2536 2602 … … 2663 2729 2664 2730 xf86InitialConfiguration(pScrn, TRUE); 2665 2731 2666 drmmode->event_context.version = 2;2667 drmmode->event_context.vblank_handler = radeon_drm_queue_handler;2668 drmmode->event_context.page_flip_handler = radeon_drm_queue_handler;2669 2670 2732 pRADEONEnt->has_page_flip_target = drmmode_probe_page_flip_target(pRADEONEnt); 2671 2733 2672 2734 drmModeFreeResources(mode_res); … … 2684 2746 info->drmmode_inited = TRUE; 2685 2747 if (pRADEONEnt->fd_wakeup_registered != serverGeneration) { 2686 2748 #if HAVE_NOTIFY_FD 2687 SetNotifyFd(pRADEONEnt->fd, drm_notify_fd, X_NOTIFY_READ, pScrn); 2749 SetNotifyFd(pRADEONEnt->fd, drm_notify_fd, X_NOTIFY_READ, 2750 &info->drmmode); 2688 2751 #else 2689 2752 AddGeneralSocket(pRADEONEnt->fd); 2690 2753 RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, 2691 drm_wakeup_handler, pScrn); 2754 drm_wakeup_handler, 2755 &info->drmmode); 2692 2756 #endif 2693 2757 pRADEONEnt->fd_wakeup_registered = serverGeneration; 2694 2758 pRADEONEnt->fd_wakeup_ref = 1; … … 2853 2917 Bool set_hw) 2854 2918 { 2855 2919 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2856 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);2857 2920 unsigned num_desired = 0, num_on = 0; 2858 2921 int c; 2859 2922 … … 2861 2924 if (set_hw) { 2862 2925 for (c = 0; c < config->num_crtc; c++) { 2863 2926 xf86CrtcPtr crtc = config->crtc[c]; 2864 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;2865 2927 2866 2928 /* Skip disabled CRTCs */ 2867 2929 if (crtc->enabled) 2868 2930 continue; 2869 2931 2870 drmmode_do_crtc_dpms(crtc, DPMSModeOff); 2871 drmModeSetCrtc(pRADEONEnt->fd, 2872 drmmode_crtc->mode_crtc->crtc_id, 2873 0, 0, 0, NULL, 0, NULL); 2874 drmmode_fb_reference(pRADEONEnt->fd, 2875 &drmmode_crtc->fb, NULL); 2932 drmmode_crtc_dpms(crtc, DPMSModeOff); 2876 2933 } 2877 2934 } 2878 2935 … … 2928 2985 } else { 2929 2986 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2930 2987 "Failed to set mode on CRTC %d\n", c); 2988 RRCrtcSet(crtc->randr_crtc, NULL, crtc->x, crtc->y, 2989 crtc->rotation, 0, NULL); 2931 2990 } 2932 2991 } else { 2933 2992 crtc->mode = crtc->desiredMode; … … 2944 3003 return FALSE; 2945 3004 } 2946 3005 3006 /* Validate leases on VT re-entry */ 3007 drmmode_validate_leases(pScrn); 3008 2947 3009 return TRUE; 2948 3010 } 2949 3011 2950 3012 Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn) 2951 3013 { 2952 3014 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3015 int i; 2953 3016 2954 3017 if (xf86_config->num_crtc) { 2955 3018 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, … … 2958 3021 return FALSE; 2959 3022 2960 3023 /* All radeons support 10 bit CLUTs. They get bypassed at depth 30. */ 2961 if (pScrn->depth != 30 && 2962 !xf86HandleColormaps(pScreen, 256, 10, 2963 NULL, NULL, 2964 CMAP_PALETTED_TRUECOLOR 2965 #if 0 /* This option messes up text mode! (eich@suse.de) */ 2966 | CMAP_LOAD_EVEN_IF_OFFSCREEN 2967 #endif 2968 | CMAP_RELOAD_ON_MODE_SWITCH)) 2969 return FALSE; 3024 if (pScrn->depth != 30) { 3025 if (!xf86HandleColormaps(pScreen, 256, 10, NULL, NULL, 3026 CMAP_PALETTED_TRUECOLOR 3027 | CMAP_RELOAD_ON_MODE_SWITCH)) 3028 return FALSE; 3029 3030 for (i = 0; i < xf86_config->num_crtc; i++) { 3031 xf86CrtcPtr crtc = xf86_config->crtc[i]; 3032 3033 drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red, 3034 crtc->gamma_green, 3035 crtc->gamma_blue, 3036 crtc->gamma_size); 3037 } 3038 } 2970 3039 } 3040 2971 3041 return TRUE; 2972 3042 } 2973 3043 … … 3103 3173 changed = TRUE; 3104 3174 } 3105 3175 3176 /* Check to see if a lessee has disappeared */ 3177 drmmode_validate_leases(scrn); 3178 3106 3179 if (changed && dixPrivateKeyRegistered(rrPrivKey)) { 3107 3180 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0) 3108 3181 RRSetChanged(xf86ScrnToScreen(scrn)); … … 3203 3276 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); 3204 3277 xf86CrtcPtr crtc = NULL; 3205 3278 drmmode_crtc_private_ptr drmmode_crtc = config->crtc[0]->driver_private; 3206 int i;3207 3279 uint32_t flip_flags = flip_sync == FLIP_ASYNC ? DRM_MODE_PAGE_FLIP_ASYNC : 0; 3208 3280 drmmode_flipdata_ptr flipdata; 3281 Bool handle_deferred = FALSE; 3209 3282 uintptr_t drm_queue_seq = 0; 3283 struct drmmode_fb *fb; 3284 int i = 0; 3210 3285 3211 flipdata = calloc(1, sizeof(drmmode_flipdata_rec)); 3286 flipdata = calloc(1, sizeof(*flipdata) + config->num_crtc * 3287 sizeof(flipdata->fb[0])); 3212 3288 if (!flipdata) { 3213 3289 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 3214 3290 "flip queue: data alloc failed.\n"); 3215 3291 goto error; 3216 3292 } 3217 3293 3218 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, 3219 radeon_pixmap_get_fb(new_front)); 3220 if (!flipdata->fb) { 3294 fb = radeon_pixmap_get_fb(new_front); 3295 if (!fb) { 3221 3296 ErrorF("Failed to get FB for flip\n"); 3222 3297 goto error; 3223 3298 } … … 3238 3313 flipdata->fe_crtc = ref_crtc; 3239 3314 3240 3315 for (i = 0; i < config->num_crtc; i++) { 3241 struct drmmode_fb *fb = flipdata->fb;3242 3243 3316 crtc = config->crtc[i]; 3244 3317 drmmode_crtc = crtc->driver_private; 3245 3318 … … 3275 3348 goto next; 3276 3349 } 3277 3350 3278 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 3279 if (!fb) { 3351 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb[i], 3352 radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap)); 3353 if (!flipdata->fb[i]) { 3280 3354 ErrorF("Failed to get FB for TearFree flip\n"); 3281 3355 goto error; 3282 3356 } 3283 3357 3284 3358 radeon_scanout_do_update(crtc, scanout_id, new_front, 3285 3359 extents); 3360 radeon_cs_flush_indirect(crtc->scrn); 3286 3361 3287 drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd, 3288 drmmode_crtc->scanout_update_pending); 3362 if (drmmode_crtc->scanout_update_pending) { 3363 radeon_drm_wait_pending_flip(crtc); 3364 handle_deferred = TRUE; 3365 radeon_drm_abort_entry(drmmode_crtc->scanout_update_pending); 3366 drmmode_crtc->scanout_update_pending = 0; 3367 } 3368 } else { 3369 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb[i], fb); 3289 3370 } 3290 3371 3291 3372 if (crtc == ref_crtc) { 3292 3373 if (drmmode_page_flip_target_absolute(pRADEONEnt, 3293 3374 drmmode_crtc, 3294 f b->handle,3375 flipdata->fb[i]->handle, 3295 3376 flip_flags, 3296 3377 drm_queue_seq, 3297 3378 target_msc) != 0) … … 3299 3380 } else { 3300 3381 if (drmmode_page_flip_target_relative(pRADEONEnt, 3301 3382 drmmode_crtc, 3302 f b->handle,3383 flipdata->fb[i]->handle, 3303 3384 flip_flags, 3304 3385 drm_queue_seq, 0) != 0) 3305 3386 goto flip_error; … … 3311 3392 } 3312 3393 3313 3394 next: 3314 drmmode_fb_reference(pRADEONEnt->fd, 3315 &drmmode_crtc->flip_pending, fb);3395 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 3396 flipdata->fb[i]); 3316 3397 drm_queue_seq = 0; 3317 3398 } 3318 3399 3400 if (handle_deferred) 3401 radeon_drm_queue_handle_deferred(ref_crtc); 3319 3402 if (flipdata->flip_count > 0) 3320 3403 return TRUE; 3321 3404 … … 3330 3413 drmmode_flip_abort(crtc, flipdata); 3331 3414 else { 3332 3415 abort(NULL, data); 3333 drmmode_fb_reference(pRADEONEnt->fd, &flipdata->fb, NULL);3334 3416 free(flipdata); 3335 3417 } 3336 3418 3337 3419 xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Page flip failed: %s\n", 3338 3420 strerror(errno)); 3421 if (handle_deferred) 3422 radeon_drm_queue_handle_deferred(ref_crtc); 3339 3423 return FALSE; 3340 3424 } -
src/drmmode_display.h
diff -Naur xf86-video-ati-18.0.1.orig/src/drmmode_display.h xf86-video-ati-18.0.1/src/drmmode_display.h
old new 56 56 } drmmode_rec, *drmmode_ptr; 57 57 58 58 typedef struct { 59 struct drmmode_fb *fb;60 59 void *event_data; 61 60 int flip_count; 62 61 unsigned int fe_frame; … … 64 63 xf86CrtcPtr fe_crtc; 65 64 radeon_drm_handler_proc handler; 66 65 radeon_drm_abort_proc abort; 66 struct drmmode_fb *fb[0]; 67 67 } drmmode_flipdata_rec, *drmmode_flipdata_ptr; 68 68 69 69 struct drmmode_fb { … … 72 72 }; 73 73 74 74 struct drmmode_scanout { 75 struct radeon_b o*bo;75 struct radeon_buffer *bo; 76 76 PixmapPtr pixmap; 77 77 int width, height; 78 78 }; … … 88 88 Bool ignore_damage; 89 89 RegionRec scanout_last_region; 90 90 unsigned scanout_id; 91 Boolscanout_update_pending;91 uintptr_t scanout_update_pending; 92 92 Bool tear_free; 93 93 94 94 PixmapPtr prime_scanout_pixmap; … … 103 103 * modeset) 104 104 */ 105 105 Bool need_modeset; 106 /* For keeping track of nested calls to drm_wait_pending_flip / 107 * drm_queue_handle_deferred 108 */ 109 int wait_flip_nesting_level; 106 110 /* A flip to this FB is pending for this CRTC */ 107 111 struct drmmode_fb *flip_pending; 108 112 /* The FB currently being scanned out by this CRTC, if any */ 109 113 struct drmmode_fb *fb; 110 111 #ifdef HAVE_PRESENT_H112 /* Deferred processing of Present vblank event */113 uint64_t present_vblank_event_id;114 uint64_t present_vblank_usec;115 unsigned present_vblank_msc;116 Bool present_flip_expected;117 #endif118 114 } drmmode_crtc_private_rec, *drmmode_crtc_private_ptr; 119 115 120 116 typedef struct { … … 139 135 int tear_free; 140 136 } drmmode_output_private_rec, *drmmode_output_private_ptr; 141 137 138 typedef struct { 139 uint32_t lessee_id; 140 } drmmode_lease_private_rec, *drmmode_lease_private_ptr; 141 142 142 143 143 enum drmmode_flip_sync { 144 144 FLIP_VSYNC, -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/evergreen_exa.c xf86-video-ati-18.0.1/src/evergreen_exa.c
old new 71 71 if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel)) 72 72 RADEON_FALLBACK(("invalid planemask\n")); 73 73 74 dst.bo = radeon_get_pixmap_bo(pPix) ;74 dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon; 75 75 dst.tiling_flags = radeon_get_pixmap_tiling(pPix); 76 76 dst.surface = radeon_get_pixmap_surface(pPix); 77 77 … … 466 466 467 467 accel_state->same_surface = FALSE; 468 468 469 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;470 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;469 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 470 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 471 471 dst_obj.surface = radeon_get_pixmap_surface(pDst); 472 472 src_obj.surface = radeon_get_pixmap_surface(pSrc); 473 473 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 474 474 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 475 if ( radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))475 if (src_obj.bo == dst_obj.bo) 476 476 accel_state->same_surface = TRUE; 477 477 478 478 src_obj.width = pSrc->drawable.width; … … 511 511 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0, 512 512 RADEON_GEM_DOMAIN_VRAM, 513 513 0); 514 if ( accel_state->copy_area_bo == NULL)514 if (!accel_state->copy_area_bo) 515 515 RADEON_FALLBACK(("temp copy surface alloc failed\n")); 516 516 517 517 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, … … 1301 1301 return FALSE; 1302 1302 1303 1303 if (pSrc) { 1304 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;1304 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 1305 1305 src_obj.surface = radeon_get_pixmap_surface(pSrc); 1306 1306 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 1307 1307 src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); … … 1311 1311 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 1312 1312 } 1313 1313 1314 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;1314 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 1315 1315 dst_obj.surface = radeon_get_pixmap_surface(pDst); 1316 1316 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 1317 1317 dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); … … 1325 1325 1326 1326 if (pMaskPicture) { 1327 1327 if (pMask) { 1328 mask_obj.bo = radeon_get_pixmap_bo(pMask) ;1328 mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon; 1329 1329 mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); 1330 1330 mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8); 1331 1331 mask_obj.surface = radeon_get_pixmap_surface(pMask); … … 1673 1673 return FALSE; 1674 1674 1675 1675 driver_priv = exaGetPixmapDriverPrivate(pDst); 1676 if (!driver_priv || !driver_priv->bo )1676 if (!driver_priv || !driver_priv->bo->bo.radeon) 1677 1677 return FALSE; 1678 1678 1679 1679 /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ 1680 copy_dst = driver_priv->bo ;1680 copy_dst = driver_priv->bo->bo.radeon; 1681 1681 copy_pitch = pDst->devKind; 1682 1682 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 1683 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {1683 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 1684 1684 flush = FALSE; 1685 if (!radeon_bo_is_busy(driver_priv->bo , &dst_domain) &&1685 if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) && 1686 1686 !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) 1687 1687 goto copy; 1688 1688 } … … 1693 1693 base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); 1694 1694 size = scratch_pitch * height * (bpp / 8); 1695 1695 scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); 1696 if ( scratch == NULL) {1696 if (!scratch) { 1697 1697 goto copy; 1698 1698 } 1699 1699 … … 1711 1711 dst_obj.height = pDst->drawable.height; 1712 1712 dst_obj.bpp = bpp; 1713 1713 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; 1714 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;1714 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 1715 1715 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 1716 1716 dst_obj.surface = radeon_get_pixmap_surface(pDst); 1717 1717 … … 1739 1739 r = TRUE; 1740 1740 size = w * bpp / 8; 1741 1741 dst = copy_dst->ptr; 1742 if (copy_dst == driver_priv->bo )1742 if (copy_dst == driver_priv->bo->bo.radeon) 1743 1743 dst += y * copy_pitch + x * bpp / 8; 1744 1744 for (i = 0; i < h; i++) { 1745 1745 memcpy(dst + i * copy_pitch, src, size); … … 1789 1789 return FALSE; 1790 1790 1791 1791 driver_priv = exaGetPixmapDriverPrivate(pSrc); 1792 if (!driver_priv || !driver_priv->bo )1792 if (!driver_priv || !driver_priv->bo->bo.radeon) 1793 1793 return FALSE; 1794 1794 1795 1795 /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ 1796 copy_src = driver_priv->bo ;1796 copy_src = driver_priv->bo->bo.radeon; 1797 1797 copy_pitch = pSrc->devKind; 1798 1798 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 1799 if (radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {1800 src_domain = radeon_bo_get_src_domain(driver_priv->bo );1799 if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 1800 src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon); 1801 1801 if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 1802 1802 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) 1803 1803 src_domain = 0; … … 1806 1806 } 1807 1807 1808 1808 if (!src_domain) 1809 radeon_bo_is_busy(driver_priv->bo , &src_domain);1809 radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain); 1810 1810 1811 1811 if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) 1812 1812 goto copy; … … 1821 1821 base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); 1822 1822 size = scratch_pitch * height * (bpp / 8); 1823 1823 scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); 1824 if ( scratch == NULL) {1824 if (!scratch) { 1825 1825 goto copy; 1826 1826 } 1827 1827 radeon_cs_space_reset_bos(info->cs); … … 1841 1841 src_obj.height = pSrc->drawable.height; 1842 1842 src_obj.bpp = bpp; 1843 1843 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 1844 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;1844 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 1845 1845 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 1846 1846 src_obj.surface = radeon_get_pixmap_surface(pSrc); 1847 1847 … … 1883 1883 } 1884 1884 r = TRUE; 1885 1885 w *= bpp / 8; 1886 if (copy_src == driver_priv->bo )1886 if (copy_src == driver_priv->bo->bo.radeon) 1887 1887 size = y * copy_pitch + x * bpp / 8; 1888 1888 else 1889 1889 size = 0; … … 1927 1927 1928 1928 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, 1929 1929 RADEON_GEM_DOMAIN_VRAM, 0); 1930 if ( accel_state->shaders_bo == NULL) {1930 if (!accel_state->shaders_bo) { 1931 1931 ErrorF("Allocating shader failed\n"); 1932 1932 return FALSE; 1933 1933 } … … 2046 2046 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2047 2047 RADEONInfoPtr info = RADEONPTR(pScrn); 2048 2048 2049 if ( info->accel_state->exa == NULL) {2049 if (!info->accel_state->exa) { 2050 2050 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); 2051 2051 return FALSE; 2052 2052 } … … 2065 2065 info->accel_state->exa->MarkSync = EVERGREENMarkSync; 2066 2066 info->accel_state->exa->WaitMarker = EVERGREENSync; 2067 2067 2068 info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;2069 2068 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; 2070 2069 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; 2071 2070 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; -
src/evergreen_state.h
diff -Naur xf86-video-ati-18.0.1.orig/src/evergreen_state.h xf86-video-ati-18.0.1/src/evergreen_state.h
old new 345 345 346 346 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index); 347 347 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index); 348 extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);349 348 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, 350 349 int depth, int usage_hint, int bitsPerPixel, 351 350 int *new_pitch); 352 351 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv); 353 extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);354 352 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix); 355 353 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p); 356 354 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle); -
src/evergreen_textured_videofuncs.c
diff -Naur xf86-video-ati-18.0.1.orig/src/evergreen_textured_videofuncs.c xf86-video-ati-18.0.1/src/evergreen_textured_videofuncs.c
old new 140 140 CLEAR (vs_const_conf); 141 141 CLEAR (ps_const_conf); 142 142 143 dst_obj.bo = radeon_get_pixmap_bo(pPixmap) ;143 dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon; 144 144 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); 145 145 dst_obj.surface = radeon_get_pixmap_surface(pPixmap); 146 146 -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/.gitignore xf86-video-ati-18.0.1/src/.gitignore
old new 1 # Add & Override for this directory and it's subdirectories 2 modes 3 parser -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/Makefile.am xf86-video-ati-18.0.1/src/Makefile.am
old new 62 62 $(RADEON_KMS_SRCS) 63 63 64 64 if GLAMOR 65 AM_CFLAGS += @LIBGLAMOR_CFLAGS@ 66 radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ 65 AM_CFLAGS += @LIBGLAMOR_CFLAGS@ @GBM_CFLAGS@ 66 radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ @GBM_LIBS@ 67 67 radeon_drv_la_SOURCES += \ 68 68 radeon_glamor_wrappers.c \ 69 69 radeon_glamor.c -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/Makefile.in xf86-video-ati-18.0.1/src/Makefile.in
old new 1 # Makefile.in generated by automake 1.15.1 from Makefile.am.2 # @configure_input@3 4 # Copyright (C) 1994-2017 Free Software Foundation, Inc.5 6 # This Makefile.in is free software; the Free Software Foundation7 # gives unlimited permission to copy and/or distribute it,8 # with or without modifications, as long as this notice is preserved.9 10 # This program is distributed in the hope that it will be useful,11 # but WITHOUT ANY WARRANTY, to the extent permitted by law; without12 # even the implied warranty of MERCHANTABILITY or FITNESS FOR A13 # PARTICULAR PURPOSE.14 15 @SET_MAKE@16 17 # Copyright 2005 Adam Jackson.18 # Copyright 2005 Red Hat, Inc.19 #20 # Permission is hereby granted, free of charge, to any person obtaining a21 # copy of this software and associated documentation files (the "Software"),22 # to deal in the Software without restriction, including without limitation23 # on the rights to use, copy, modify, merge, publish, distribute, sub24 # license, and/or sell copies of the Software, and to permit persons to whom25 # the Software is furnished to do so, subject to the following conditions:26 #27 # The above copyright notice and this permission notice (including the next28 # paragraph) shall be included in all copies or substantial portions of the29 # Software.30 #31 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR32 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,33 # FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL34 # ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER35 # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN36 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.37 38 # this is obnoxious:39 # -module lets us name the module exactly how we want40 # -avoid-version prevents gratuitous .0.0.0 version numbers on the end41 # _ladir passes a dummy rpath to libtool so the thing will actually link42 # TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.43 44 VPATH = @srcdir@45 am__is_gnu_make = { \46 if test -z '$(MAKELEVEL)'; then \47 false; \48 elif test -n '$(MAKE_HOST)'; then \49 true; \50 elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \51 true; \52 else \53 false; \54 fi; \55 }56 am__make_running_with_option = \57 case $${target_option-} in \58 ?) ;; \59 *) echo "am__make_running_with_option: internal error: invalid" \60 "target option '$${target_option-}' specified" >&2; \61 exit 1;; \62 esac; \63 has_opt=no; \64 sane_makeflags=$$MAKEFLAGS; \65 if $(am__is_gnu_make); then \66 sane_makeflags=$$MFLAGS; \67 else \68 case $$MAKEFLAGS in \69 *\\[\ \ ]*) \70 bs=\\; \71 sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \72 | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \73 esac; \74 fi; \75 skip_next=no; \76 strip_trailopt () \77 { \78 flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \79 }; \80 for flg in $$sane_makeflags; do \81 test $$skip_next = yes && { skip_next=no; continue; }; \82 case $$flg in \83 *=*|--*) continue;; \84 -*I) strip_trailopt 'I'; skip_next=yes;; \85 -*I?*) strip_trailopt 'I';; \86 -*O) strip_trailopt 'O'; skip_next=yes;; \87 -*O?*) strip_trailopt 'O';; \88 -*l) strip_trailopt 'l'; skip_next=yes;; \89 -*l?*) strip_trailopt 'l';; \90 -[dEDm]) skip_next=yes;; \91 -[JT]) skip_next=yes;; \92 esac; \93 case $$flg in \94 *$$target_option*) has_opt=yes; break;; \95 esac; \96 done; \97 test $$has_opt = yes98 am__make_dryrun = (target_option=n; $(am__make_running_with_option))99 am__make_keepgoing = (target_option=k; $(am__make_running_with_option))100 pkgdatadir = $(datadir)/@PACKAGE@101 pkgincludedir = $(includedir)/@PACKAGE@102 pkglibdir = $(libdir)/@PACKAGE@103 pkglibexecdir = $(libexecdir)/@PACKAGE@104 am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd105 install_sh_DATA = $(install_sh) -c -m 644106 install_sh_PROGRAM = $(install_sh) -c107 install_sh_SCRIPT = $(install_sh) -c108 INSTALL_HEADER = $(INSTALL_DATA)109 transform = $(program_transform_name)110 NORMAL_INSTALL = :111 PRE_INSTALL = :112 POST_INSTALL = :113 NORMAL_UNINSTALL = :114 PRE_UNINSTALL = :115 POST_UNINSTALL = :116 build_triplet = @build@117 host_triplet = @host@118 @LIBUDEV_TRUE@am__append_1 = $(LIBUDEV_LIBS)119 @GLAMOR_TRUE@am__append_2 = @LIBGLAMOR_CFLAGS@120 @GLAMOR_TRUE@am__append_3 = @LIBGLAMOR_LIBS@121 @GLAMOR_TRUE@am__append_4 = \122 @GLAMOR_TRUE@ radeon_glamor_wrappers.c \123 @GLAMOR_TRUE@ radeon_glamor.c124 125 subdir = src126 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4127 am__aclocal_m4_deps = $(top_srcdir)/m4/libtool.m4 \128 $(top_srcdir)/m4/ltoptions.m4 $(top_srcdir)/m4/ltsugar.m4 \129 $(top_srcdir)/m4/ltversion.m4 $(top_srcdir)/m4/lt~obsolete.m4 \130 $(top_srcdir)/configure.ac131 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \132 $(ACLOCAL_M4)133 DIST_COMMON = $(srcdir)/Makefile.am $(am__DIST_COMMON)134 mkinstalldirs = $(install_sh) -d135 CONFIG_HEADER = $(top_builddir)/config.h136 CONFIG_CLEAN_FILES =137 CONFIG_CLEAN_VPATH_FILES =138 am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;139 am__vpath_adj = case $$p in \140 $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \141 *) f=$$p;; \142 esac;143 am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;144 am__install_max = 40145 am__nobase_strip_setup = \146 srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`147 am__nobase_strip = \148 for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"149 am__nobase_list = $(am__nobase_strip_setup); \150 for p in $$list; do echo "$$p $$p"; done | \151 sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \152 $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \153 if (++n[$$2] == $(am__install_max)) \154 { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \155 END { for (dir in files) print dir, files[dir] }'156 am__base_list = \157 sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \158 sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'159 am__uninstall_files_from_dir = { \160 test -z "$$files" \161 || { test ! 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xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/r600_exa.c xf86-video-ati-18.0.1/src/r600_exa.c
old new 150 150 if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel)) 151 151 RADEON_FALLBACK(("invalid planemask\n")); 152 152 153 dst.bo = radeon_get_pixmap_bo(pPix) ;153 dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon; 154 154 dst.tiling_flags = radeon_get_pixmap_tiling(pPix); 155 155 dst.surface = radeon_get_pixmap_surface(pPix); 156 156 … … 534 534 535 535 accel_state->same_surface = FALSE; 536 536 537 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;538 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;537 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 538 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 539 539 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 540 540 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 541 541 src_obj.surface = radeon_get_pixmap_surface(pSrc); 542 542 dst_obj.surface = radeon_get_pixmap_surface(pDst); 543 if ( radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))543 if (src_obj.bo == dst_obj.bo) 544 544 accel_state->same_surface = TRUE; 545 545 546 546 src_obj.width = pSrc->drawable.width; … … 575 575 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align, 576 576 RADEON_GEM_DOMAIN_VRAM, 577 577 0); 578 if ( accel_state->copy_area_bo == NULL)578 if (!accel_state->copy_area_bo) 579 579 RADEON_FALLBACK(("temp copy surface alloc failed\n")); 580 580 581 581 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, … … 1344 1344 return FALSE; 1345 1345 1346 1346 if (pSrc) { 1347 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;1347 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 1348 1348 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 1349 1349 src_obj.surface = radeon_get_pixmap_surface(pSrc); 1350 1350 src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); … … 1354 1354 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 1355 1355 } 1356 1356 1357 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;1357 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 1358 1358 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 1359 1359 dst_obj.surface = radeon_get_pixmap_surface(pDst); 1360 1360 dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); … … 1368 1368 1369 1369 if (pMaskPicture) { 1370 1370 if (pMask) { 1371 mask_obj.bo = radeon_get_pixmap_bo(pMask) ;1371 mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon; 1372 1372 mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); 1373 1373 mask_obj.surface = radeon_get_pixmap_surface(pMask); 1374 1374 mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8); … … 1700 1700 return FALSE; 1701 1701 1702 1702 driver_priv = exaGetPixmapDriverPrivate(pDst); 1703 if (!driver_priv || !driver_priv->bo )1703 if (!driver_priv || !driver_priv->bo->bo.radeon) 1704 1704 return FALSE; 1705 1705 1706 1706 /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ 1707 copy_dst = driver_priv->bo ;1707 copy_dst = driver_priv->bo->bo.radeon; 1708 1708 copy_pitch = pDst->devKind; 1709 1709 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 1710 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {1710 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 1711 1711 flush = FALSE; 1712 if (!radeon_bo_is_busy(driver_priv->bo , &dst_domain) &&1712 if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) && 1713 1713 !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) 1714 1714 goto copy; 1715 1715 } … … 1723 1723 base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); 1724 1724 size = scratch_pitch * height * (bpp / 8); 1725 1725 scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); 1726 if ( scratch == NULL) {1726 if (!scratch) { 1727 1727 goto copy; 1728 1728 } 1729 1729 … … 1741 1741 dst_obj.height = pDst->drawable.height; 1742 1742 dst_obj.bpp = bpp; 1743 1743 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; 1744 dst_obj.bo = radeon_get_pixmap_bo(pDst) ;1744 dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon; 1745 1745 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); 1746 1746 dst_obj.surface = radeon_get_pixmap_surface(pDst); 1747 1747 … … 1769 1769 r = TRUE; 1770 1770 size = w * bpp / 8; 1771 1771 dst = copy_dst->ptr; 1772 if (copy_dst == driver_priv->bo )1772 if (copy_dst == driver_priv->bo->bo.radeon) 1773 1773 dst += y * copy_pitch + x * bpp / 8; 1774 1774 for (i = 0; i < h; i++) { 1775 1775 memcpy(dst + i * copy_pitch, src, size); … … 1819 1819 return FALSE; 1820 1820 1821 1821 driver_priv = exaGetPixmapDriverPrivate(pSrc); 1822 if (!driver_priv || !driver_priv->bo )1822 if (!driver_priv || !driver_priv->bo->bo.radeon) 1823 1823 return FALSE; 1824 1824 1825 1825 /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ 1826 copy_src = driver_priv->bo ;1826 copy_src = driver_priv->bo->bo.radeon; 1827 1827 copy_pitch = pSrc->devKind; 1828 1828 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 1829 if (radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {1830 src_domain = radeon_bo_get_src_domain(driver_priv->bo );1829 if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 1830 src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon); 1831 1831 if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 1832 1832 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) 1833 1833 src_domain = 0; … … 1836 1836 } 1837 1837 1838 1838 if (!src_domain) 1839 radeon_bo_is_busy(driver_priv->bo , &src_domain);1839 radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain); 1840 1840 1841 1841 if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) 1842 1842 goto copy; … … 1847 1847 base_align = drmmode_get_base_align(pScrn, (bpp / 8), 0); 1848 1848 size = scratch_pitch * height * (bpp / 8); 1849 1849 scratch = radeon_bo_open(info->bufmgr, 0, size, base_align, RADEON_GEM_DOMAIN_GTT, 0); 1850 if ( scratch == NULL) {1850 if (!scratch) { 1851 1851 goto copy; 1852 1852 } 1853 1853 radeon_cs_space_reset_bos(info->cs); … … 1867 1867 src_obj.height = pSrc->drawable.height; 1868 1868 src_obj.bpp = bpp; 1869 1869 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 1870 src_obj.bo = radeon_get_pixmap_bo(pSrc) ;1870 src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon; 1871 1871 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); 1872 1872 src_obj.surface = radeon_get_pixmap_surface(pSrc); 1873 1873 … … 1909 1909 } 1910 1910 r = TRUE; 1911 1911 w *= bpp / 8; 1912 if (copy_src == driver_priv->bo )1912 if (copy_src == driver_priv->bo->bo.radeon) 1913 1913 size = y * copy_pitch + x * bpp / 8; 1914 1914 else 1915 1915 size = 0; … … 1960 1960 1961 1961 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, 1962 1962 RADEON_GEM_DOMAIN_VRAM, 0); 1963 if ( accel_state->shaders_bo == NULL) {1963 if (!accel_state->shaders_bo) { 1964 1964 ErrorF("Allocating shader failed\n"); 1965 1965 return FALSE; 1966 1966 } … … 2025 2025 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2026 2026 RADEONInfoPtr info = RADEONPTR(pScrn); 2027 2027 2028 if ( info->accel_state->exa == NULL) {2028 if (!info->accel_state->exa) { 2029 2029 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); 2030 2030 return FALSE; 2031 2031 } … … 2044 2044 info->accel_state->exa->MarkSync = R600MarkSync; 2045 2045 info->accel_state->exa->WaitMarker = R600Sync; 2046 2046 2047 info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;2048 2047 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; 2049 2048 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; 2050 2049 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/r600_state.h xf86-video-ati-18.0.1/src/r600_state.h
old new 316 316 317 317 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index); 318 318 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index); 319 extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);320 319 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, 321 320 int depth, int usage_hint, int bitsPerPixel, 322 321 int *new_pitch); 323 322 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv); 324 extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);325 323 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix); 326 324 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p); 327 325 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle); -
src/r600_textured_videofuncs.c
diff -Naur xf86-video-ati-18.0.1.orig/src/r600_textured_videofuncs.c xf86-video-ati-18.0.1/src/r600_textured_videofuncs.c
old new 152 152 CLEAR (vs_conf); 153 153 CLEAR (ps_conf); 154 154 155 dst_obj.bo = radeon_get_pixmap_bo(pPixmap) ;155 dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon; 156 156 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); 157 157 dst_obj.surface = radeon_get_pixmap_surface(pPixmap); 158 158 -
src/radeon_bo_helper.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_bo_helper.c xf86-video-ati-18.0.1/src/radeon_bo_helper.c
old new 28 28 #include "radeon_glamor.h" 29 29 #include "radeon_bo_gem.h" 30 30 31 32 #ifdef USE_GLAMOR 33 34 static uint32_t 35 radeon_get_gbm_format(int depth, int bitsPerPixel) 36 { 37 switch (depth) { 38 #ifdef GBM_FORMAT_R8 39 case 8: 40 return GBM_FORMAT_R8; 41 #endif 42 case 16: 43 return GBM_FORMAT_RGB565; 44 case 32: 45 return GBM_FORMAT_ARGB8888; 46 case 30: 47 return GBM_FORMAT_XRGB2101010; 48 case 24: 49 if (bitsPerPixel == 32) 50 return GBM_FORMAT_XRGB8888; 51 /* fall through */ 52 default: 53 ErrorF("%s: Unsupported depth/bpp %d/%d\n", __func__, depth, 54 bitsPerPixel); 55 return ~0U; 56 } 57 } 58 59 #endif /* USE_GLAMOR */ 60 61 31 62 static const unsigned MicroBlockTable[5][3][2] = { 32 63 /*linear tiled square-tiled */ 33 64 {{32, 1}, {8, 4}, {0, 0}}, /* 8 bits per pixel */ … … 59 90 } 60 91 } 61 92 93 static unsigned eg_tile_split_opp(unsigned tile_split) 94 { 95 switch (tile_split) { 96 case 0: tile_split = 64; break; 97 case 1: tile_split = 128; break; 98 case 2: tile_split = 256; break; 99 case 3: tile_split = 512; break; 100 default: 101 case 4: tile_split = 1024; break; 102 case 5: tile_split = 2048; break; 103 case 6: tile_split = 4096; break; 104 } 105 return tile_split; 106 } 107 108 Bool 109 radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface, 110 int width, int height, int cpp, uint32_t tiling_flags, 111 int usage_hint) 112 { 113 memset(surface, 0, sizeof(struct radeon_surface)); 114 115 surface->npix_x = width; 116 /* need to align height to 8 for old kernel */ 117 surface->npix_y = RADEON_ALIGN(height, 8); 118 surface->npix_z = 1; 119 surface->blk_w = 1; 120 surface->blk_h = 1; 121 surface->blk_d = 1; 122 surface->array_size = 1; 123 surface->last_level = 0; 124 surface->bpe = cpp; 125 surface->nsamples = 1; 126 if (height < 128) { 127 /* disable 2d tiling for small surface to work around 128 * the fact that ddx align height to 8 pixel for old 129 * obscure reason i can't remember 130 */ 131 tiling_flags &= ~RADEON_TILING_MACRO; 132 } 133 134 surface->flags = RADEON_SURF_SCANOUT | RADEON_SURF_HAS_TILE_MODE_INDEX | 135 RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 136 137 if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) { 138 surface->flags |= RADEON_SURF_ZBUFFER; 139 surface->flags |= RADEON_SURF_SBUFFER; 140 } 141 142 if ((tiling_flags & RADEON_TILING_MACRO)) { 143 surface->flags = RADEON_SURF_CLR(surface->flags, MODE); 144 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 145 } else if ((tiling_flags & RADEON_TILING_MICRO)) { 146 surface->flags = RADEON_SURF_CLR(surface->flags, MODE); 147 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 148 } else 149 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 150 151 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 152 surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & 153 RADEON_TILING_EG_BANKW_MASK; 154 surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & 155 RADEON_TILING_EG_BANKH_MASK; 156 surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & 157 RADEON_TILING_EG_TILE_SPLIT_MASK); 158 if (surface->flags & RADEON_SURF_SBUFFER) { 159 surface->stencil_tile_split = 160 (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & 161 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 162 } 163 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & 164 RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 165 } 166 167 if (radeon_surface_best(info->surf_man, surface)) 168 return FALSE; 169 170 if (radeon_surface_init(info->surf_man, surface)) 171 return FALSE; 172 173 return TRUE; 174 } 175 62 176 /* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that 63 177 * can hold it. 64 178 */ 65 struct radeon_b o*179 struct radeon_buffer * 66 180 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, 67 181 int usage_hint, int bitsPerPixel, int *new_pitch, 68 182 struct radeon_surface *new_surface, uint32_t *new_tiling) … … 73 187 int cpp = bitsPerPixel / 8; 74 188 uint32_t tiling = 0, flags = 0; 75 189 struct radeon_surface surface; 76 struct radeon_b o*bo;190 struct radeon_buffer *bo; 77 191 int domain = RADEON_GEM_DOMAIN_VRAM; 192 193 #ifdef USE_GLAMOR 194 if (info->use_glamor && 195 !(usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP && 196 info->shadow_primary)) { 197 uint32_t bo_use = GBM_BO_USE_RENDERING; 198 uint32_t gbm_format = radeon_get_gbm_format(depth, bitsPerPixel); 199 200 if (gbm_format == ~0U) 201 return NULL; 202 203 bo = calloc(1, sizeof(struct radeon_buffer)); 204 if (!bo) 205 return NULL; 206 207 bo->ref_count = 1; 208 209 if (bitsPerPixel == pScrn->bitsPerPixel) 210 bo_use |= GBM_BO_USE_SCANOUT; 211 212 if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP && 213 info->shadow_primary) || 214 (usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED) 215 bo_use |= GBM_BO_USE_LINEAR; 216 217 bo->bo.gbm = gbm_bo_create(info->gbm, width, height, gbm_format, bo_use); 218 if (!bo->bo.gbm) { 219 free(bo); 220 return NULL; 221 } 222 223 bo->flags |= RADEON_BO_FLAGS_GBM; 224 225 if (new_pitch) 226 *new_pitch = gbm_bo_get_stride(bo->bo.gbm); 227 228 return bo; 229 } 230 #endif 231 78 232 if (usage_hint) { 79 233 if (info->allowColorTiling) { 80 234 if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO) … … 107 261 pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp; 108 262 base_align = drmmode_get_base_align(pScrn, cpp, tiling); 109 263 size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE); 110 memset(&surface, 0, sizeof(struct radeon_surface));111 264 112 if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { 113 if (width) { 114 surface.npix_x = width; 115 /* need to align height to 8 for old kernel */ 116 surface.npix_y = RADEON_ALIGN(height, 8); 117 surface.npix_z = 1; 118 surface.blk_w = 1; 119 surface.blk_h = 1; 120 surface.blk_d = 1; 121 surface.array_size = 1; 122 surface.last_level = 0; 123 surface.bpe = cpp; 124 surface.nsamples = 1; 125 if (height < 128) { 126 /* disable 2d tiling for small surface to work around 127 * the fact that ddx align height to 8 pixel for old 128 * obscure reason i can't remember 129 */ 130 tiling &= ~RADEON_TILING_MACRO; 131 } 132 surface.flags = RADEON_SURF_SCANOUT; 133 /* we are requiring a recent enough libdrm version */ 134 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 135 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 136 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 137 if ((tiling & RADEON_TILING_MICRO)) { 138 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 139 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 140 } 141 if ((tiling & RADEON_TILING_MACRO)) { 142 surface.flags = RADEON_SURF_CLR(surface.flags, MODE); 143 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 144 } 145 if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) { 146 surface.flags |= RADEON_SURF_ZBUFFER; 147 surface.flags |= RADEON_SURF_SBUFFER; 148 } 149 if (radeon_surface_best(info->surf_man, &surface)) { 150 return NULL; 151 } 152 if (radeon_surface_init(info->surf_man, &surface)) { 153 return NULL; 154 } 155 size = surface.bo_size; 156 base_align = surface.bo_alignment; 157 pitch = surface.level[0].pitch_bytes; 158 tiling = 0; 159 switch (surface.level[0].mode) { 160 case RADEON_SURF_MODE_2D: 161 tiling |= RADEON_TILING_MACRO; 162 tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 163 tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 164 tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 165 if (surface.tile_split) 166 tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 167 tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT; 168 break; 169 case RADEON_SURF_MODE_1D: 170 tiling |= RADEON_TILING_MICRO; 171 break; 172 default: 173 break; 174 } 175 } 265 if (width && info->surf_man) { 266 if (!radeon_surface_initialize(info, &surface, width, height, cpp, 267 tiling, usage_hint)) 268 return NULL; 269 270 size = surface.bo_size; 271 base_align = surface.bo_alignment; 272 pitch = surface.level[0].pitch_bytes; 273 tiling = 0; 274 switch (surface.level[0].mode) { 275 case RADEON_SURF_MODE_2D: 276 tiling |= RADEON_TILING_MACRO; 277 tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT; 278 tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT; 279 tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 280 if (surface.tile_split) 281 tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; 282 if (surface.flags & RADEON_SURF_SBUFFER) 283 tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT; 284 break; 285 case RADEON_SURF_MODE_1D: 286 tiling |= RADEON_TILING_MICRO; 287 break; 288 default: 289 break; 176 290 } 177 291 292 if (new_surface) 293 *new_surface = surface; 294 } 295 178 296 if (tiling) 179 297 flags |= RADEON_GEM_NO_CPU_ACCESS; 180 298 181 bo = radeon_bo_open(info->bufmgr, 0, size, base_align, 182 domain, flags); 299 bo = calloc(1, sizeof(struct radeon_buffer)); 300 if (!bo) 301 return NULL; 302 303 bo->ref_count = 1; 304 bo->bo.radeon = radeon_bo_open(info->bufmgr, 0, size, base_align, 305 domain, flags); 183 306 184 if (bo && tiling && radeon_bo_set_tiling(bo , tiling, pitch) == 0)307 if (bo && tiling && radeon_bo_set_tiling(bo->bo.radeon, tiling, pitch) == 0) 185 308 *new_tiling = tiling; 186 309 187 *new_surface = surface;188 310 *new_pitch = pitch; 189 311 return bo; 190 312 } 191 313 314 315 /* Flush and wait for the BO to become idle */ 316 void 317 radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo) 318 { 319 RADEONInfoPtr info = RADEONPTR(scrn); 320 321 if (info->use_glamor) { 322 radeon_glamor_finish(scrn); 323 return; 324 } 325 326 radeon_cs_flush_indirect(scrn); 327 radeon_bo_wait(bo->bo.radeon); 328 } 329 330 192 331 /* Clear the pixmap contents to black */ 193 332 void 194 333 radeon_pixmap_clear(PixmapPtr pixmap) … … 213 352 /* Get GEM handle for the pixmap */ 214 353 Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle) 215 354 { 216 struct radeon_b o*bo = radeon_get_pixmap_bo(pixmap);355 struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap); 217 356 #ifdef USE_GLAMOR 218 357 ScreenPtr screen = pixmap->drawable.pScreen; 219 358 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); … … 221 360 RADEONInfoPtr info = RADEONPTR(scrn); 222 361 #endif 223 362 224 if (bo ) {225 *handle = bo-> handle;363 if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM)) { 364 *handle = bo->bo.radeon->handle; 226 365 return TRUE; 227 366 } 228 367 … … 305 444 return TRUE; 306 445 } 307 446 308 static unsigned eg_tile_split_opp(unsigned tile_split)309 {310 switch (tile_split) {311 case 0: tile_split = 64; break;312 case 1: tile_split = 128; break;313 case 2: tile_split = 256; break;314 case 3: tile_split = 512; break;315 default:316 case 4: tile_split = 1024; break;317 case 5: tile_split = 2048; break;318 case 6: tile_split = 4096; break;319 }320 return tile_split;321 }322 323 447 Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle, 324 448 struct radeon_surface *surface) 325 449 { 326 450 ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen); 327 451 RADEONInfoPtr info = RADEONPTR(pScrn); 328 struct radeon_b o*bo;452 struct radeon_buffer *bo; 329 453 int ihandle = (int)(long)fd_handle; 330 454 uint32_t size = ppix->devKind * ppix->drawable.height; 331 455 Bool ret = FALSE; 332 456 333 bo = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);457 bo = (struct radeon_buffer *)calloc(1, sizeof(struct radeon_buffer)); 334 458 if (!bo) 335 459 goto error; 336 460 337 memset(surface, 0, sizeof(struct radeon_surface)); 461 #ifdef USE_GLAMOR 462 if (info->use_glamor) { 463 struct gbm_import_fd_data data; 464 uint32_t bo_use = GBM_BO_USE_RENDERING; 465 466 data.format = radeon_get_gbm_format(ppix->drawable.depth, 467 ppix->drawable.bitsPerPixel); 468 if (data.format == ~0U) 469 goto error; 338 470 471 bo->ref_count = 1; 472 473 data.fd = ihandle; 474 data.width = ppix->drawable.width; 475 data.height = ppix->drawable.height; 476 data.stride = ppix->devKind; 477 478 if (ppix->drawable.bitsPerPixel == pScrn->bitsPerPixel) 479 bo_use |= GBM_BO_USE_SCANOUT; 480 481 bo->bo.gbm = gbm_bo_import(info->gbm, GBM_BO_IMPORT_FD, &data, bo_use); 482 if (!bo->bo.gbm) 483 goto error; 484 485 bo->flags |= RADEON_BO_FLAGS_GBM; 486 487 if (!radeon_glamor_create_textured_pixmap(ppix, bo)) { 488 radeon_buffer_unref(&bo); 489 return FALSE; 490 } 491 492 ret = radeon_set_pixmap_bo(ppix, bo); 493 /* radeon_set_pixmap_bo increments ref_count if it succeeds */ 494 radeon_buffer_unref(&bo); 495 return ret; 496 } 497 #endif 498 499 bo->bo.radeon = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size); 500 if (!bo) 501 goto error; 502 503 bo->ref_count = 1; 339 504 ret = radeon_set_pixmap_bo(ppix, bo); 340 505 if (!ret) 341 506 goto error; 342 507 343 if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { 508 if (surface) { 509 struct radeon_exa_pixmap_priv *driver_priv; 344 510 uint32_t tiling_flags; 345 511 346 #ifdef USE_GLAMOR 347 if (info->use_glamor) { 348 tiling_flags = radeon_get_pixmap_private(ppix)->tiling_flags; 349 } else 350 #endif 351 { 352 struct radeon_exa_pixmap_priv *driver_priv; 353 354 driver_priv = exaGetPixmapDriverPrivate(ppix); 355 tiling_flags = driver_priv->tiling_flags; 356 } 512 driver_priv = exaGetPixmapDriverPrivate(ppix); 513 tiling_flags = driver_priv->tiling_flags; 357 514 358 surface->npix_x = ppix->drawable.width; 359 surface->npix_y = ppix->drawable.height; 360 surface->npix_z = 1; 361 surface->blk_w = 1; 362 surface->blk_h = 1; 363 surface->blk_d = 1; 364 surface->array_size = 1; 365 surface->bpe = ppix->drawable.bitsPerPixel / 8; 366 surface->nsamples = 1; 367 /* we are requiring a recent enough libdrm version */ 368 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; 369 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 370 if (tiling_flags & RADEON_TILING_MACRO) 371 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 372 else if (tiling_flags & RADEON_TILING_MICRO) 373 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 374 else 375 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 376 surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 377 surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 378 surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK); 379 surface->stencil_tile_split = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 380 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 381 if (radeon_surface_best(info->surf_man, surface)) { 382 ret = FALSE; 383 goto error; 384 } 385 if (radeon_surface_init(info->surf_man, surface)) { 515 if (!radeon_surface_initialize(info, surface, ppix->drawable.width, 516 ppix->drawable.height, 517 ppix->drawable.bitsPerPixel / 8, 518 tiling_flags, 0)) { 386 519 ret = FALSE; 387 520 goto error; 388 521 } 522 389 523 /* we have to post hack the surface to reflect the actual size 390 524 of the shared pixmap */ 391 525 surface->level[0].pitch_bytes = ppix->devKind; … … 396 530 close(ihandle); 397 531 /* we have a reference from the alloc and one from set pixmap bo, 398 532 drop one */ 399 radeon_b o_unref(bo);533 radeon_buffer_unref(&bo); 400 534 return ret; 401 535 } -
src/radeon_bo_helper.h
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_bo_helper.h xf86-video-ati-18.0.1/src/radeon_bo_helper.h
old new 23 23 #ifndef RADEON_BO_HELPER_H 24 24 #define RADEON_BO_HELPER_H 1 25 25 26 extern struct radeon_bo* 26 #ifdef USE_GLAMOR 27 #include <gbm.h> 28 #endif 29 30 #define RADEON_BO_FLAGS_GBM 0x1 31 32 struct radeon_buffer { 33 union { 34 #ifdef USE_GLAMOR 35 struct gbm_bo *gbm; 36 #endif 37 struct radeon_bo *radeon; 38 } bo; 39 uint32_t ref_count; 40 uint32_t flags; 41 }; 42 43 extern struct radeon_buffer * 27 44 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, 28 45 int usage_hint, int bitsPerPixel, int *new_pitch, 29 46 struct radeon_surface *new_surface, uint32_t *new_tiling); 30 47 31 48 extern void 49 radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo); 50 51 extern void 32 52 radeon_pixmap_clear(PixmapPtr pixmap); 33 53 34 54 extern uint32_t … … 57 77 return drawable->pScreen->GetWindowPixmap((WindowPtr)drawable); 58 78 } 59 79 80 static inline void 81 radeon_buffer_ref(struct radeon_buffer *buffer) 82 { 83 buffer->ref_count++; 84 } 85 86 static inline void 87 radeon_buffer_unref(struct radeon_buffer **buffer) 88 { 89 struct radeon_buffer *buf = *buffer; 90 91 if (!buf) 92 return; 93 94 if (buf->ref_count > 1) { 95 buf->ref_count--; 96 return; 97 } 98 99 #ifdef USE_GLAMOR 100 if (buf->flags & RADEON_BO_FLAGS_GBM) { 101 gbm_bo_destroy(buf->bo.gbm); 102 } else 103 #endif 104 { 105 radeon_bo_unmap(buf->bo.radeon); 106 radeon_bo_unref(buf->bo.radeon); 107 } 108 109 free(buf); 110 *buffer = NULL; 111 } 112 60 113 #endif /* RADEON_BO_HELPER_H */ -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_dri2.c xf86-video-ati-18.0.1/src/radeon_dri2.c
old new 79 79 static Bool 80 80 radeon_get_flink_name(RADEONEntPtr pRADEONEnt, PixmapPtr pixmap, uint32_t *name) 81 81 { 82 struct radeon_b o*bo = radeon_get_pixmap_bo(pixmap);82 struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap); 83 83 struct drm_gem_flink flink; 84 84 85 if (bo) 86 return radeon_gem_get_kernel_name(bo, name) == 0; 85 if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM) && 86 radeon_gem_get_kernel_name(bo->bo.radeon, name) == 0) 87 return TRUE; 87 88 88 89 if (radeon_get_pixmap_handle(pixmap, &flink.handle)) { 89 90 if (drmIoctl(pRADEONEnt->fd, DRM_IOCTL_GEM_FLINK, &flink) != 0) … … 233 234 flags | RADEON_CREATE_PIXMAP_DRI2); 234 235 } 235 236 237 if (!pixmap) 238 return NULL; 239 236 240 buffers = calloc(1, sizeof *buffers); 237 if ( buffers == NULL)241 if (!buffers) 238 242 goto error; 239 243 240 if (pixmap) { 241 if (!info->use_glamor) { 242 info->exa_force_create = TRUE; 243 exaMoveInPixmap(pixmap); 244 info->exa_force_create = FALSE; 245 if (exaGetPixmapDriverPrivate(pixmap) == NULL) { 246 /* this happen if pixmap is non accelerable */ 247 goto error; 248 } 249 } else if (is_glamor_pixmap) { 250 pixmap = radeon_glamor_set_pixmap_bo(drawable, pixmap); 251 pixmap->refcnt++; 252 } 253 254 if (!radeon_get_flink_name(pRADEONEnt, pixmap, &buffers->name)) 244 if (!info->use_glamor) { 245 info->exa_force_create = TRUE; 246 exaMoveInPixmap(pixmap); 247 info->exa_force_create = FALSE; 248 if (!exaGetPixmapDriverPrivate(pixmap)) { 249 /* this happen if pixmap is non accelerable */ 255 250 goto error; 251 } 252 } else if (is_glamor_pixmap) { 253 pixmap = radeon_glamor_set_pixmap_bo(drawable, pixmap); 254 pixmap->refcnt++; 256 255 } 257 256 257 if (!radeon_get_flink_name(pRADEONEnt, pixmap, &buffers->name)) 258 goto error; 259 258 260 privates = calloc(1, sizeof(struct dri2_buffer_priv)); 259 if ( privates == NULL)261 if (!privates) 260 262 goto error; 261 263 262 264 buffers->attachment = attachment; 263 if (pixmap) { 264 buffers->pitch = pixmap->devKind; 265 buffers->cpp = cpp; 266 } 265 buffers->pitch = pixmap->devKind; 266 buffers->cpp = cpp; 267 267 buffers->driverPrivate = privates; 268 268 buffers->format = format; 269 269 buffers->flags = 0; /* not tiled */ … … 275 275 276 276 error: 277 277 free(buffers); 278 if (pixmap) 279 (*pScreen->DestroyPixmap)(pixmap); 278 (*pScreen->DestroyPixmap)(pixmap); 280 279 return NULL; 281 280 } 282 281 … … 338 337 Bool vsync; 339 338 Bool translate = FALSE; 340 339 int off_x = 0, off_y = 0; 341 PixmapPtr dst_ppix;342 340 343 dst_ppix = dst_private->pixmap;344 341 src_drawable = &src_private->pixmap->drawable; 345 342 dst_drawable = &dst_private->pixmap->drawable; 346 343 … … 357 354 dst_drawable = DRI2UpdatePrime(drawable, dest_buffer); 358 355 if (!dst_drawable) 359 356 return; 360 dst_ppix = (PixmapPtr)dst_drawable;361 357 if (dst_drawable != drawable) 362 358 translate = TRUE; 363 359 } else … … 381 377 (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0); 382 378 ValidateGC(dst_drawable, gc); 383 379 384 /* If this is a full buffer swap or frontbuffer flush, throttle on the385 * previous one386 */387 if (dst_private->attachment == DRI2BufferFrontLeft) {388 if (REGION_NUM_RECTS(region) == 1) {389 BoxPtr extents = REGION_EXTENTS(pScreen, region);390 391 if (extents->x1 == 0 && extents->y1 == 0 &&392 extents->x2 == drawable->width &&393 extents->y2 == drawable->height) {394 struct radeon_bo *bo = radeon_get_pixmap_bo(dst_ppix);395 396 if (bo)397 radeon_bo_wait(bo);398 }399 }400 }401 402 380 vsync = info->accel_state->vsync; 403 404 381 /* Driver option "SwapbuffersWait" defines if we vsync DRI2 copy-swaps. */ 405 382 info->accel_state->vsync = info->swapBuffersWait; 406 383 info->accel_state->force = TRUE; … … 743 720 { 744 721 struct dri2_buffer_priv *front_priv = front->driverPrivate; 745 722 struct dri2_buffer_priv *back_priv = back->driverPrivate; 746 struct radeon_bo *front_bo, *back_bo; 747 ScreenPtr screen; 748 RADEONInfoPtr info; 723 ScreenPtr screen = draw->pScreen; 724 RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(screen)); 749 725 RegionRec region; 750 726 int tmp; 751 727 … … 760 736 front->name = back->name; 761 737 back->name = tmp; 762 738 763 /* Swap pixmap bos */ 764 front_bo = radeon_get_pixmap_bo(front_priv->pixmap); 765 back_bo = radeon_get_pixmap_bo(back_priv->pixmap); 766 radeon_set_pixmap_bo(front_priv->pixmap, back_bo); 767 radeon_set_pixmap_bo(back_priv->pixmap, front_bo); 768 769 /* Do we need to update the Screen? */ 770 screen = draw->pScreen; 771 info = RADEONPTR(xf86ScreenToScrn(screen)); 772 if (front_bo == info->front_bo) { 773 radeon_bo_ref(back_bo); 774 radeon_bo_unref(info->front_bo); 775 info->front_bo = back_bo; 776 radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), back_bo); 777 } 739 /* Swap pixmap privates */ 740 #ifdef USE_GLAMOR 741 if (info->use_glamor) { 742 struct radeon_pixmap *front_pix, *back_pix; 743 744 front_pix = radeon_get_pixmap_private(front_priv->pixmap); 745 back_pix = radeon_get_pixmap_private(back_priv->pixmap); 746 radeon_set_pixmap_private(front_priv->pixmap, back_pix); 747 radeon_set_pixmap_private(back_priv->pixmap, front_pix); 748 749 radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap); 750 } else 751 #endif 752 { 753 struct radeon_exa_pixmap_priv driver_priv = *(struct radeon_exa_pixmap_priv*) 754 exaGetPixmapDriverPrivate(front_priv->pixmap); 778 755 779 radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap); 756 *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(front_priv->pixmap) = 757 *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(back_priv->pixmap); 758 *(struct radeon_exa_pixmap_priv*)exaGetPixmapDriverPrivate(back_priv->pixmap) = 759 driver_priv; 760 } 780 761 781 762 DamageRegionProcessPending(&front_priv->pixmap->drawable); 782 763 } … … 942 923 xf86CrtcPtr crtc = radeon_dri2_drawable_crtc(draw, TRUE); 943 924 944 925 /* Drawable not displayed, make up a value */ 945 if ( crtc == NULL) {926 if (!crtc) { 946 927 *ust = 0; 947 928 *msc = 0; 948 929 return TRUE; … … 987 968 988 969 scrn = crtc->scrn; 989 970 pRADEONEnt = RADEONEntPriv(scrn); 971 drmmode_crtc = event_info->crtc->driver_private; 990 972 ret = drmmode_get_current_ust(pRADEONEnt->fd, &drm_now); 991 973 if (ret) { 992 974 xf86DrvMsg(scrn->scrnIndex, X_ERROR, 993 975 "%s cannot get current time\n", __func__); 994 976 if (event_info->drm_queue_seq) 995 radeon_drm_queue_handler(pRADEONEnt->fd, 0, 0, 0, 996 (void*)event_info->drm_queue_seq); 977 drmmode_crtc->drmmode->event_context. 978 vblank_handler(pRADEONEnt->fd, 0, 0, 0, 979 (void*)event_info->drm_queue_seq); 997 980 else 998 981 radeon_dri2_frame_event_handler(crtc, 0, 0, data); 999 982 return 0; … … 1002 985 * calculate the frame number from current time 1003 986 * that would come from CRTC if it were running 1004 987 */ 1005 drmmode_crtc = event_info->crtc->driver_private;1006 988 delta_t = drm_now - (CARD64)drmmode_crtc->dpms_last_ust; 1007 989 delta_seq = delta_t * drmmode_crtc->dpms_last_fps; 1008 990 delta_seq /= 1000000; 1009 991 frame = (CARD64)drmmode_crtc->dpms_last_seq + delta_seq; 1010 992 if (event_info->drm_queue_seq) 1011 radeon_drm_queue_handler(pRADEONEnt->fd, frame, drm_now / 1000000, 1012 drm_now % 1000000, 1013 (void*)event_info->drm_queue_seq); 993 drmmode_crtc->drmmode->event_context. 994 vblank_handler(pRADEONEnt->fd, frame, drm_now / 1000000, 995 drm_now % 1000000, 996 (void*)event_info->drm_queue_seq); 1014 997 else 1015 998 radeon_dri2_frame_event_handler(crtc, frame, drm_now, data); 1016 999 return 0; … … 1053 1036 remainder &= 0xffffffff; 1054 1037 1055 1038 /* Drawable not visible, return immediately */ 1056 if ( crtc == NULL)1039 if (!crtc) 1057 1040 goto out_complete; 1058 1041 1059 1042 msc_delta = radeon_get_msc_delta(draw, crtc); … … 1212 1195 radeon_dri2_ref_buffer(back); 1213 1196 1214 1197 /* either off-screen or CRTC not usable... just complete the swap */ 1215 if ( crtc == NULL)1198 if (!crtc) 1216 1199 goto blit_fallback; 1217 1200 1218 1201 msc_delta = radeon_get_msc_delta(draw, crtc); -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_dri3.c xf86-video-ati-18.0.1/src/radeon_dri3.c
old new 169 169 170 170 if (priv) { 171 171 radeon_set_pixmap_private(pixmap, priv); 172 pixmap->usage_hint |= RADEON_CREATE_PIXMAP_DRI2; 172 173 return pixmap; 173 174 } 174 175 … … 213 214 { 214 215 struct radeon_bo *bo; 215 216 int fd; 216 217 bo = radeon_get_pixmap_bo(pixmap);218 if (!bo) {219 217 #ifdef USE_GLAMOR 220 221 218 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 219 RADEONInfoPtr info = RADEONPTR(scrn); 222 220 223 224 221 if (info->use_glamor) 222 return glamor_fd_from_pixmap(screen, pixmap, stride, size); 225 223 #endif 226 224 225 bo = radeon_get_pixmap_bo(pixmap)->bo.radeon; 226 if (!bo) { 227 227 exaMoveInPixmap(pixmap); 228 bo = radeon_get_pixmap_bo(pixmap) ;228 bo = radeon_get_pixmap_bo(pixmap)->bo.radeon; 229 229 if (!bo) 230 230 return -1; 231 231 } -
src/radeon_drm_queue.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_drm_queue.c xf86-video-ati-18.0.1/src/radeon_drm_queue.c
old new 40 40 41 41 struct radeon_drm_queue_entry { 42 42 struct xorg_list list; 43 uint64_t usec; 43 44 uint64_t id; 44 45 uintptr_t seq; 45 46 void *data; … … 47 48 xf86CrtcPtr crtc; 48 49 radeon_drm_handler_proc handler; 49 50 radeon_drm_abort_proc abort; 51 unsigned int frame; 50 52 }; 51 53 52 54 static int radeon_drm_queue_refcnt; 53 55 static struct xorg_list radeon_drm_queue; 56 static struct xorg_list radeon_drm_flip_signalled; 57 static struct xorg_list radeon_drm_vblank_signalled; 54 58 static uintptr_t radeon_drm_queue_seq; 55 59 56 60 57 61 /* 58 * Handlea DRM event62 * Process a DRM event 59 63 */ 60 void 61 radeon_drm_queue_handler(int fd, unsigned int frame, unsigned int sec, 62 unsigned int usec, void *user_ptr) 64 static void 65 radeon_drm_queue_handle_one(struct radeon_drm_queue_entry *e) 63 66 { 64 uintptr_t seq = (uintptr_t)user_ptr; 65 struct radeon_drm_queue_entry *e, *tmp; 67 xorg_list_del(&e->list); 68 if (e->handler) { 69 e->handler(e->crtc, e->frame, e->usec, e->data); 70 } else 71 e->abort(e->crtc, e->data); 72 free(e); 73 } 74 75 static void 76 radeon_drm_queue_handler(struct xorg_list *signalled, unsigned int frame, 77 unsigned int sec, unsigned int usec, void *user_ptr) 78 { 79 uintptr_t seq = (uintptr_t)user_ptr; 80 struct radeon_drm_queue_entry *e, *tmp; 66 81 67 68 69 xorg_list_del(&e->list);70 if (e->handler)71 e->handler(e->crtc, frame,72 (uint64_t)sec * 1000000 + usec,73 e->data); 74 else75 e->abort(e->crtc, e->data);76 free(e);77 break;78 }82 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { 83 if (e->seq == seq) { 84 if (!e->handler) { 85 e->abort(e->crtc, e->data); 86 break; 87 } 88 89 xorg_list_del(&e->list); 90 e->usec = (uint64_t)sec * 1000000 + usec; 91 e->frame = frame; 92 xorg_list_append(&e->list, signalled); 93 break; 79 94 } 95 } 96 } 97 98 /* 99 * Signal a DRM page flip event 100 */ 101 static void 102 radeon_drm_page_flip_handler(int fd, unsigned int frame, unsigned int sec, 103 unsigned int usec, void *user_ptr) 104 { 105 radeon_drm_queue_handler(&radeon_drm_flip_signalled, frame, sec, usec, 106 user_ptr); 107 } 108 109 /* 110 * Signal a DRM vblank event 111 */ 112 static void 113 radeon_drm_vblank_handler(int fd, unsigned int frame, unsigned int sec, 114 unsigned int usec, void *user_ptr) 115 { 116 radeon_drm_queue_handler(&radeon_drm_vblank_signalled, frame, sec, usec, 117 user_ptr); 118 } 119 120 /* 121 * Handle deferred DRM vblank events 122 * 123 * This function must be called after radeon_drm_wait_pending_flip, once 124 * it's safe to attempt queueing a flip again 125 */ 126 void 127 radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc) 128 { 129 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 130 struct radeon_drm_queue_entry *e, *tmp; 131 132 if (drmmode_crtc->wait_flip_nesting_level == 0 || 133 --drmmode_crtc->wait_flip_nesting_level > 0) 134 return; 135 136 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) { 137 drmmode_crtc_private_ptr drmmode_crtc = e->crtc->driver_private; 138 139 if (drmmode_crtc->wait_flip_nesting_level == 0) 140 radeon_drm_queue_handle_one(e); 141 } 80 142 } 81 143 82 144 /* … … 150 212 { 151 213 struct radeon_drm_queue_entry *e, *tmp; 152 214 215 if (seq == RADEON_DRM_QUEUE_ERROR) 216 return; 217 218 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) { 219 if (e->seq == seq) { 220 radeon_drm_abort_one(e); 221 return; 222 } 223 } 224 153 225 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_queue, list) { 154 226 if (e->seq == seq) { 155 227 radeon_drm_abort_one(e); … … 175 247 } 176 248 177 249 /* 250 * drmHandleEvent wrapper 251 */ 252 int 253 radeon_drm_handle_event(int fd, drmEventContext *event_context) 254 { 255 struct radeon_drm_queue_entry *e, *tmp; 256 int r; 257 258 r = drmHandleEvent(fd, event_context); 259 260 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_flip_signalled, list) 261 radeon_drm_queue_handle_one(e); 262 263 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_vblank_signalled, list) { 264 drmmode_crtc_private_ptr drmmode_crtc = e->crtc->driver_private; 265 266 if (drmmode_crtc->wait_flip_nesting_level == 0) 267 radeon_drm_queue_handle_one(e); 268 } 269 270 return r; 271 } 272 273 /* 274 * Wait for pending page flip on given CRTC to complete 275 */ 276 void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc) 277 { 278 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 279 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 280 struct radeon_drm_queue_entry *e, *tmp; 281 282 drmmode_crtc->wait_flip_nesting_level++; 283 284 xorg_list_for_each_entry_safe(e, tmp, &radeon_drm_flip_signalled, list) 285 radeon_drm_queue_handle_one(e); 286 287 while (drmmode_crtc->flip_pending 288 && radeon_drm_handle_event(pRADEONEnt->fd, 289 &drmmode_crtc->drmmode->event_context) > 0); 290 } 291 292 /* 178 293 * Initialize the DRM event queue 179 294 */ 180 295 void 181 radeon_drm_queue_init( )296 radeon_drm_queue_init(ScrnInfoPtr scrn) 182 297 { 298 RADEONInfoPtr info = RADEONPTR(scrn); 299 drmmode_ptr drmmode = &info->drmmode; 300 301 drmmode->event_context.version = 2; 302 drmmode->event_context.vblank_handler = radeon_drm_vblank_handler; 303 drmmode->event_context.page_flip_handler = radeon_drm_page_flip_handler; 304 183 305 if (radeon_drm_queue_refcnt++) 184 306 return; 185 307 186 308 xorg_list_init(&radeon_drm_queue); 309 xorg_list_init(&radeon_drm_flip_signalled); 310 xorg_list_init(&radeon_drm_vblank_signalled); 187 311 } 188 312 189 313 /* -
src/radeon_drm_queue.h
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_drm_queue.h xf86-video-ati-18.0.1/src/radeon_drm_queue.h
old new 40 40 uint64_t usec, void *data); 41 41 typedef void (*radeon_drm_abort_proc)(xf86CrtcPtr crtc, void *data); 42 42 43 void radeon_drm_queue_handler(int fd, unsigned int frame, 44 unsigned int tv_sec, unsigned int tv_usec, 45 void *user_ptr); 43 void radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc); 46 44 uintptr_t radeon_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client, 47 45 uint64_t id, void *data, 48 46 radeon_drm_handler_proc handler, … … 50 48 void radeon_drm_abort_client(ClientPtr client); 51 49 void radeon_drm_abort_entry(uintptr_t seq); 52 50 void radeon_drm_abort_id(uint64_t id); 53 void radeon_drm_queue_init(); 51 int radeon_drm_handle_event(int fd, drmEventContext *event_context); 52 void radeon_drm_wait_pending_flip(xf86CrtcPtr crtc); 53 void radeon_drm_queue_init(ScrnInfoPtr scrn); 54 54 void radeon_drm_queue_close(ScrnInfoPtr scrn); 55 55 56 56 #endif /* _RADEON_DRM_QUEUE_H_ */ -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_exa.c xf86-video-ati-18.0.1/src/radeon_exa.c
old new 150 150 */ 151 151 Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t) 152 152 { 153 if ( t == NULL)153 if (!t) 154 154 return TRUE; 155 155 /* the shaders don't handle scaling either */ 156 156 return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1); … … 184 184 return FALSE; 185 185 186 186 /* if we have more refs than just the BO then flush */ 187 if (radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {187 if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 188 188 flush = TRUE; 189 189 190 190 if (can_fail) { 191 possible_domains = radeon_bo_get_src_domain(driver_priv->bo );191 possible_domains = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon); 192 192 if (possible_domains == RADEON_GEM_DOMAIN_VRAM) 193 193 return FALSE; /* use DownloadFromScreen */ 194 194 } … … 196 196 197 197 /* if the BO might end up in VRAM, prefer DownloadFromScreen */ 198 198 if (can_fail && (possible_domains & RADEON_GEM_DOMAIN_VRAM)) { 199 radeon_bo_is_busy(driver_priv->bo , ¤t_domain);199 radeon_bo_is_busy(driver_priv->bo->bo.radeon, ¤t_domain); 200 200 201 201 if (current_domain & possible_domains) { 202 202 if (current_domain == RADEON_GEM_DOMAIN_VRAM) … … 209 209 radeon_cs_flush_indirect(pScrn); 210 210 211 211 /* flush IB */ 212 ret = radeon_bo_map(driver_priv->bo , 1);212 ret = radeon_bo_map(driver_priv->bo->bo.radeon, 1); 213 213 if (ret) { 214 214 FatalError("failed to map pixmap %d\n", ret); 215 215 return FALSE; 216 216 } 217 217 driver_priv->bo_mapped = TRUE; 218 218 219 pPix->devPrivate.ptr = driver_priv->bo-> ptr;219 pPix->devPrivate.ptr = driver_priv->bo->bo.radeon->ptr; 220 220 221 221 return TRUE; 222 222 } … … 229 229 if (!driver_priv || !driver_priv->bo_mapped) 230 230 return; 231 231 232 radeon_bo_unmap(driver_priv->bo );232 radeon_bo_unmap(driver_priv->bo->bo.radeon); 233 233 driver_priv->bo_mapped = FALSE; 234 234 pPix->devPrivate.ptr = NULL; 235 235 } 236 236 237 237 238 void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align)239 {240 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);241 RADEONInfoPtr info = RADEONPTR(pScrn);242 struct radeon_exa_pixmap_priv *new_priv;243 244 if (size != 0 && !info->exa_force_create &&245 info->exa_pixmaps == FALSE)246 return NULL;247 248 new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));249 if (!new_priv)250 return NULL;251 252 if (size == 0)253 return new_priv;254 255 new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, align,256 RADEON_GEM_DOMAIN_VRAM, 0);257 if (!new_priv->bo) {258 free(new_priv);259 ErrorF("Failed to alloc memory\n");260 return NULL;261 }262 263 return new_priv;264 265 }266 267 238 void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, 268 239 int depth, int usage_hint, int bitsPerPixel, 269 240 int *new_pitch) … … 306 277 if (!driverPriv) 307 278 return; 308 279 309 if (driver_priv->bo) 310 radeon_bo_unref(driver_priv->bo); 280 radeon_buffer_unref(&driver_priv->bo); 311 281 drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL); 312 282 free(driverPriv); 313 283 } … … 316 286 { 317 287 struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(ppix); 318 288 319 if (!radeon_share_pixmap_backing(driver_priv->bo , fd_handle))289 if (!radeon_share_pixmap_backing(driver_priv->bo->bo.radeon, fd_handle)) 320 290 return FALSE; 321 291 322 292 driver_priv->shared = TRUE; -
src/radeon_exa_funcs.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_exa_funcs.c xf86-video-ati-18.0.1/src/radeon_exa_funcs.c
old new 138 138 radeon_cs_space_reset_bos(info->cs); 139 139 140 140 driver_priv = exaGetPixmapDriverPrivate(pPix); 141 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); 141 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 142 RADEON_GEM_DOMAIN_VRAM); 142 143 143 144 ret = radeon_cs_space_check(info->cs); 144 145 if (ret) … … 146 147 147 148 driver_priv = exaGetPixmapDriverPrivate(pPix); 148 149 if (driver_priv) { 149 info->state_2d.dst_bo = driver_priv->bo ;150 info->state_2d.dst_bo = driver_priv->bo->bo.radeon; 150 151 info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM; 151 152 } 152 153 … … 256 257 radeon_cs_space_reset_bos(info->cs); 257 258 258 259 driver_priv = exaGetPixmapDriverPrivate(pSrc); 259 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 260 info->state_2d.src_bo = driver_priv->bo; 260 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 261 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 262 info->state_2d.src_bo = driver_priv->bo->bo.radeon; 261 263 262 264 driver_priv = exaGetPixmapDriverPrivate(pDst); 263 info->state_2d.dst_bo = driver_priv->bo ;265 info->state_2d.dst_bo = driver_priv->bo->bo.radeon; 264 266 info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM; 265 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, info->state_2d.dst_domain); 267 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 268 info->state_2d.dst_domain); 266 269 267 270 ret = radeon_cs_space_check(info->cs); 268 271 if (ret) … … 328 331 329 332 if (src_bo && dst_bo) { 330 333 BEGIN_ACCEL_RELOC(6, 2); 331 } else if (src_bo && dst_bo == NULL) {334 } else if (src_bo && !dst_bo) { 332 335 BEGIN_ACCEL_RELOC(6, 1); 333 336 } else { 334 337 BEGIN_RING(2*6); … … 389 392 return FALSE; 390 393 391 394 driver_priv = exaGetPixmapDriverPrivate(pDst); 392 if (!driver_priv || !driver_priv->bo )395 if (!driver_priv || !driver_priv->bo->bo.radeon) 393 396 return FALSE; 394 397 395 398 #if X_BYTE_ORDER == X_BIG_ENDIAN … … 404 407 #endif 405 408 406 409 /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */ 407 copy_dst = driver_priv->bo ;410 copy_dst = driver_priv->bo->bo.radeon; 408 411 copy_pitch = pDst->devKind; 409 412 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 410 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {413 if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 411 414 flush = FALSE; 412 if (!radeon_bo_is_busy(driver_priv->bo , &dst_domain) &&415 if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) && 413 416 !(dst_domain & RADEON_GEM_DOMAIN_VRAM)) 414 417 goto copy; 415 418 } … … 420 423 421 424 size = scratch_pitch * h; 422 425 scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0); 423 if ( scratch == NULL) {426 if (!scratch) { 424 427 goto copy; 425 428 } 426 429 radeon_cs_space_reset_bos(info->cs); … … 446 449 r = TRUE; 447 450 size = w * bpp / 8; 448 451 dst = copy_dst->ptr; 449 if (copy_dst == driver_priv->bo )452 if (copy_dst == driver_priv->bo->bo.radeon) 450 453 dst += y * copy_pitch + x * bpp / 8; 451 454 for (i = 0; i < h; i++) { 452 455 RADEONCopySwap(dst + i * copy_pitch, (uint8_t*)src, size, swap); … … 458 461 RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype); 459 462 RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset); 460 463 RADEON_SWITCH_TO_2D(); 461 RADEONBlitChunk(pScrn, scratch, driver_priv->bo , datatype, scratch_pitch << 16,464 RADEONBlitChunk(pScrn, scratch, driver_priv->bo->bo.radeon, datatype, scratch_pitch << 16, 462 465 dst_pitch_offset, 0, 0, x, y, w, h, 463 466 RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_VRAM); 464 467 } … … 493 496 return FALSE; 494 497 495 498 driver_priv = exaGetPixmapDriverPrivate(pSrc); 496 if (!driver_priv || !driver_priv->bo )499 if (!driver_priv || !driver_priv->bo->bo.radeon) 497 500 return FALSE; 498 501 499 502 #if X_BYTE_ORDER == X_BIG_ENDIAN … … 508 511 #endif 509 512 510 513 /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */ 511 copy_src = driver_priv->bo ;514 copy_src = driver_priv->bo->bo.radeon; 512 515 copy_pitch = pSrc->devKind; 513 516 if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) { 514 if (radeon_bo_is_referenced_by_cs(driver_priv->bo , info->cs)) {515 src_domain = radeon_bo_get_src_domain(driver_priv->bo );517 if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) { 518 src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon); 516 519 if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 517 520 (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) 518 521 src_domain = 0; … … 521 524 } 522 525 523 526 if (!src_domain) 524 radeon_bo_is_busy(driver_priv->bo , &src_domain);527 radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain); 525 528 526 529 if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM) 527 530 goto copy; 528 531 } 529 532 size = scratch_pitch * h; 530 533 scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0); 531 if ( scratch == NULL) {534 if (!scratch) { 532 535 goto copy; 533 536 } 534 537 radeon_cs_space_reset_bos(info->cs); … … 541 544 RADEONGetDatatypeBpp(pSrc->drawable.bitsPerPixel, &datatype); 542 545 RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset); 543 546 RADEON_SWITCH_TO_2D(); 544 RADEONBlitChunk(pScrn, driver_priv->bo , scratch, datatype, src_pitch_offset,545 547 RADEONBlitChunk(pScrn, driver_priv->bo->bo.radeon, scratch, datatype, 548 src_pitch_offset, scratch_pitch << 16, x, y, 0, 0, w, h, 546 549 RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 547 550 RADEON_GEM_DOMAIN_GTT); 548 551 copy_src = scratch; … … 561 564 } 562 565 r = TRUE; 563 566 w *= bpp / 8; 564 if (copy_src == driver_priv->bo )567 if (copy_src == driver_priv->bo->bo.radeon) 565 568 size = y * copy_pitch + x * bpp / 8; 566 569 else 567 570 size = 0; … … 581 584 { 582 585 RINFO_FROM_SCREEN(pScreen); 583 586 584 if ( info->accel_state->exa == NULL) {587 if (!info->accel_state->exa) { 585 588 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n"); 586 589 return FALSE; 587 590 } … … 638 641 } 639 642 #endif 640 643 641 info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;642 644 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; 643 645 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; 644 646 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; -
src/radeon_exa_render.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_exa_render.c xf86-video-ati-18.0.1/src/radeon_exa_render.c
old new 630 630 return FALSE; 631 631 pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; 632 632 633 if (pMask != NULL) {633 if (pMask) { 634 634 if (!R100TextureSetup(pMaskPicture, pMask, 1)) 635 635 return FALSE; 636 636 pp_cntl |= RADEON_TEX_1_ENABLE; … … 992 992 return FALSE; 993 993 pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; 994 994 995 if (pMask != NULL) {995 if (pMask) { 996 996 if (!R200TextureSetup(pMaskPicture, pMask, 1)) 997 997 return FALSE; 998 998 pp_cntl |= RADEON_TEX_1_ENABLE; … … 1484 1484 return FALSE; 1485 1485 txenable = R300_TEX_0_ENABLE; 1486 1486 1487 if (pMask != NULL) {1487 if (pMask) { 1488 1488 if (!R300TextureSetup(pMaskPicture, pMask, 1)) 1489 1489 return FALSE; 1490 1490 txenable |= R300_TEX_1_ENABLE; -
src/radeon_exa_shared.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_exa_shared.c xf86-video-ati-18.0.1/src/radeon_exa_shared.c
old new 129 129 struct radeon_bo *bo; 130 130 exaMoveInPixmap(pPix); 131 131 132 bo = radeon_get_pixmap_bo(pPix) ;132 bo = radeon_get_pixmap_bo(pPix)->bo.radeon; 133 133 134 134 if (radeon_bo_map(bo, 1)) { 135 135 pScreen->DestroyPixmap(pPix); -
src/radeon_exa_shared.h
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_exa_shared.h xf86-video-ati-18.0.1/src/radeon_exa_shared.h
old new 66 66 { 67 67 struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); 68 68 69 radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain); 69 radeon_cs_space_add_persistent_bo(cs, driver_priv->bo->bo.radeon, 70 read_domains, write_domain); 70 71 } 71 72 72 73 extern void radeon_ib_discard(ScrnInfoPtr pScrn); -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_glamor.c xf86-video-ati-18.0.1/src/radeon_glamor.c
old new 50 50 Bool 51 51 radeon_glamor_create_screen_resources(ScreenPtr screen) 52 52 { 53 PixmapPtr screen_pixmap = screen->GetScreenPixmap(screen); 53 54 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 54 55 RADEONInfoPtr info = RADEONPTR(scrn); 55 56 … … 61 62 return FALSE; 62 63 #endif 63 64 64 if (!glamor_egl_create_textured_screen(screen, 65 info->front_bo->handle, 66 scrn->displayWidth * 67 info->pixel_bytes)) 68 return FALSE; 69 70 return TRUE; 65 return radeon_glamor_create_textured_pixmap(screen_pixmap, 66 info->front_buffer); 71 67 } 72 68 73 69 … … 136 132 } 137 133 #endif 138 134 135 info->gbm = gbm_create_device(pRADEONEnt->fd); 136 if (!info->gbm) { 137 xf86DrvMsg(scrn->scrnIndex, X_ERROR, 138 "gbm_create_device returned NULL\n"); 139 return FALSE; 140 } 141 139 142 /* Load glamor module */ 140 143 if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) { 141 144 version = xf86GetModuleVersion(glamor_module); … … 164 167 } 165 168 166 169 Bool 167 radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_ pixmap *priv)170 radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo) 168 171 { 169 return glamor_egl_create_textured_pixmap(pixmap, priv->bo->handle, 170 pixmap->devKind); 172 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 173 RADEONInfoPtr info = RADEONPTR(scrn); 174 175 if (!info->use_glamor) 176 return TRUE; 177 178 if (bo->flags & RADEON_BO_FLAGS_GBM) { 179 return glamor_egl_create_textured_pixmap_from_gbm_bo(pixmap, 180 bo->bo.gbm 181 #if XORG_VERSION_CURRENT > XORG_VERSION_NUMERIC(1,19,99,903,0) 182 , FALSE 183 #endif 184 ); 185 } else { 186 return glamor_egl_create_textured_pixmap(pixmap, 187 bo->bo.radeon->handle, 188 pixmap->devKind); 189 } 171 190 } 172 191 173 192 static Bool radeon_glamor_destroy_pixmap(PixmapPtr pixmap) … … 179 198 #endif 180 199 181 200 if (pixmap->refcnt == 1) { 182 if (pixmap->devPrivate.ptr) {183 struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);184 185 if (bo)186 radeon_bo_unmap(bo);187 }188 189 201 #ifdef HAVE_GLAMOR_EGL_DESTROY_TEXTURED_PIXMAP 190 202 glamor_egl_destroy_textured_pixmap(pixmap); 191 203 #endif … … 214 226 struct radeon_pixmap *priv; 215 227 PixmapPtr pixmap, new_pixmap = NULL; 216 228 229 if (!xf86GetPixFormat(scrn, depth)) 230 return NULL; 231 217 232 if (!RADEON_CREATE_PIXMAP_SHARED(usage)) { 218 233 if (info->shadow_primary) { 219 234 if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP) … … 242 257 int stride; 243 258 244 259 priv = calloc(1, sizeof (struct radeon_pixmap)); 245 if ( priv == NULL)260 if (!priv) 246 261 goto fallback_pixmap; 247 262 248 263 priv->bo = radeon_alloc_pixmap_bo(scrn, w, h, depth, usage, 249 264 pixmap->drawable.bitsPerPixel, 250 &stride, 251 &priv->surface, 265 &stride, NULL, 252 266 &priv->tiling_flags); 253 267 if (!priv->bo) 254 268 goto fallback_priv; … … 257 271 258 272 screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL); 259 273 260 if (!radeon_glamor_create_textured_pixmap(pixmap, priv ))274 if (!radeon_glamor_create_textured_pixmap(pixmap, priv->bo)) 261 275 goto fallback_glamor; 262 276 263 277 pixmap->devPrivate.ptr = NULL; … … 287 301 * afterwards. 288 302 */ 289 303 new_pixmap = glamor_create_pixmap(screen, w, h, depth, usage); 290 radeon_b o_unref(priv->bo);304 radeon_buffer_unref(&priv->bo); 291 305 fallback_priv: 292 306 free(priv); 293 307 fallback_pixmap: … … 388 402 { 389 403 ScreenPtr screen = pixmap->drawable.pScreen; 390 404 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 391 struct radeon_surface surface;392 struct radeon_pixmap *priv;393 405 394 if (!radeon_set_shared_pixmap_backing(pixmap, handle, &surface))406 if (!radeon_set_shared_pixmap_backing(pixmap, handle, NULL)) 395 407 return FALSE; 396 408 397 priv = radeon_get_pixmap_private(pixmap); 398 priv->surface = surface; 399 400 if (!radeon_glamor_create_textured_pixmap(pixmap, priv)) { 409 if (!radeon_glamor_create_textured_pixmap(pixmap, 410 radeon_get_pixmap_bo(pixmap))) { 401 411 xf86DrvMsg(scrn->scrnIndex, X_ERROR, 402 412 "Failed to get PRIME drawable for glamor pixmap.\n"); 403 413 return FALSE; -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_glamor.h xf86-video-ati-18.0.1/src/radeon_glamor.h
old new 33 33 34 34 #ifdef USE_GLAMOR 35 35 36 #ifndef HAVE_GLAMOR_FINISH 37 #include <GL/gl.h> 38 #endif 39 40 #include <gbm.h> 41 36 42 #define GLAMOR_FOR_XORG 1 37 43 #include <glamor.h> 38 44 … … 65 71 Bool radeon_glamor_create_screen_resources(ScreenPtr screen); 66 72 void radeon_glamor_free_screen(int scrnIndex, int flags); 67 73 68 Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_ pixmap *priv);74 Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo); 69 75 void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst); 70 76 PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap); 71 77 72 78 XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt); 73 79 80 static inline void 81 radeon_glamor_finish(ScrnInfoPtr scrn) 82 { 83 RADEONInfoPtr info = RADEONPTR(scrn); 84 85 #if HAVE_GLAMOR_FINISH 86 glamor_finish(scrn->pScreen); 87 #else 88 glamor_block_handler(scrn->pScreen); 89 glFinish(); 90 #endif 91 92 info->gpu_flushed++; 93 } 94 74 95 #else 75 96 76 97 static inline Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { return FALSE; } … … 79 100 static inline Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { return FALSE; } 80 101 static inline void radeon_glamor_free_screen(int scrnIndex, int flags) { } 81 102 82 static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_ pixmap *priv) { return TRUE; }103 static inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo) { return TRUE; } 83 104 84 105 static inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {} 85 106 static inline PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap) { return pixmap; } … … 87 108 static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; } 88 109 89 110 static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; } 111 112 static inline void radeon_glamor_finish(ScrnInfoPtr pScrn) { } 113 90 114 #endif 91 115 92 116 #endif /* RADEON_GLAMOR_H */ -
src/radeon_glamor_wrappers.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_glamor_wrappers.c xf86-video-ati-18.0.1/src/radeon_glamor_wrappers.c
old new 55 55 PixmapPtr pixmap, struct radeon_pixmap *priv, 56 56 Bool need_sync) 57 57 { 58 struct radeon_b o*bo = priv->bo;58 struct radeon_buffer *bo = priv->bo; 59 59 int ret; 60 60 61 /* When falling back to swrast, flush all pending operations */62 if (need_sync) {63 glamor_block_handler(scrn->pScreen);64 info->gpu_flushed++;65 }66 67 61 if (!pixmap->devPrivate.ptr) { 68 ret = radeon_bo_map(bo, 1); 62 /* When falling back to swrast, flush all pending operations */ 63 if (need_sync) { 64 glamor_block_handler(scrn->pScreen); 65 info->gpu_flushed++; 66 } 67 68 ret = radeon_bo_map(bo->bo.radeon, 1); 69 69 if (ret) { 70 70 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 71 71 "%s: bo map (tiling_flags %d) failed: %s\n", … … 75 75 return FALSE; 76 76 } 77 77 78 pixmap->devPrivate.ptr = bo->ptr; 79 info->gpu_synced = info->gpu_flushed; 80 } else if (need_sync) { 81 radeon_bo_wait(bo); 82 info->gpu_synced = info->gpu_flushed; 83 } 78 pixmap->devPrivate.ptr = bo->bo.radeon->ptr; 79 } else if (need_sync) 80 radeon_finish(scrn, bo); 81 82 info->gpu_synced = info->gpu_flushed; 84 83 85 84 return TRUE; 86 85 } … … 133 132 static Bool 134 133 radeon_glamor_prepare_access_gpu(struct radeon_pixmap *priv) 135 134 { 136 return priv != NULL;135 return !!priv; 137 136 } 138 137 139 138 static void … … 202 201 PixmapPtr pixmap; 203 202 struct radeon_pixmap *priv; 204 203 205 if ( picture->pDrawable == NULL)204 if (!picture->pDrawable) 206 205 return TRUE; 207 206 208 207 pixmap = get_drawable_pixmap(picture->pDrawable); -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon.h xf86-video-ati-18.0.1/src/radeon.h
old new 83 83 #include "radeon_dri2.h" 84 84 #include "drmmode_display.h" 85 85 #include "radeon_surface.h" 86 #include "radeon_bo_helper.h" 86 87 87 88 /* Render support */ 88 89 #ifdef RENDER … … 300 301 #define CURSOR_WIDTH_CIK 128 301 302 #define CURSOR_HEIGHT_CIK 128 302 303 303 304 304 #ifdef USE_GLAMOR 305 305 306 306 struct radeon_pixmap { 307 struct radeon_surface surface;308 309 307 uint_fast32_t gpu_read; 310 308 uint_fast32_t gpu_write; 311 309 312 struct radeon_b o*bo;310 struct radeon_buffer *bo; 313 311 struct drmmode_fb *fb; 314 312 315 313 uint32_t tiling_flags; … … 335 333 336 334 337 335 struct radeon_exa_pixmap_priv { 338 struct radeon_b o*bo;336 struct radeon_buffer *bo; 339 337 struct drmmode_fb *fb; 340 338 uint32_t tiling_flags; 341 339 struct radeon_surface surface; … … 569 567 570 568 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 571 569 struct radeon_2d_state state_2d; 572 struct radeon_b o *front_bo;570 struct radeon_buffer *front_buffer; 573 571 struct radeon_bo_manager *bufmgr; 574 572 struct radeon_cs_manager *csm; 575 573 struct radeon_cs *cs; … … 608 606 unsigned hwcursor_disabled; 609 607 610 608 #ifdef USE_GLAMOR 609 struct gbm_device *gbm; 610 611 611 struct { 612 612 CreateGCProcPtr SavedCreateGC; 613 613 RegionPtr (*SavedCopyArea)(DrawablePtr, DrawablePtr, GCPtr, int, int, … … 645 645 extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 646 646 647 647 /* radeon_bo_helper.c */ 648 extern Bool 649 radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface, 650 int width, int height, int cpp, uint32_t tiling_flags, 651 int usage_hint); 652 648 653 extern Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle); 649 654 650 655 /* radeon_commonfuncs.c */ … … 703 708 704 709 static inline struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix) 705 710 { 706 #ifdef USE_GLAMOR 707 RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); 711 struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); 708 712 709 if (info->use_glamor) { 710 struct radeon_pixmap *priv; 711 priv = radeon_get_pixmap_private(pPix); 712 return priv ? &priv->surface : NULL; 713 } else 714 #endif 715 { 716 struct radeon_exa_pixmap_priv *driver_priv; 717 driver_priv = exaGetPixmapDriverPrivate(pPix); 718 return &driver_priv->surface; 719 } 720 721 return NULL; 713 return &driver_priv->surface; 722 714 } 723 715 724 716 uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); 725 717 726 static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_b o*bo)718 static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_buffer *bo) 727 719 { 728 720 ScrnInfoPtr scrn = xf86ScreenToScrn(pPix->drawable.pScreen); 729 721 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); … … 734 726 struct radeon_pixmap *priv; 735 727 736 728 priv = radeon_get_pixmap_private(pPix); 737 if ( priv == NULL && bo == NULL)729 if (!priv && !bo) 738 730 return TRUE; 739 731 740 732 if (priv) { … … 742 734 if (priv->bo == bo) 743 735 return TRUE; 744 736 745 radeon_bo_unref(priv->bo); 737 radeon_buffer_unref(&priv->bo); 738 priv->handle_valid = FALSE; 746 739 } 747 740 748 741 drmmode_fb_reference(pRADEONEnt->fd, &priv->fb, NULL); … … 754 747 } 755 748 756 749 if (bo) { 757 uint32_t pitch;758 759 750 if (!priv) { 760 751 priv = calloc(1, sizeof (struct radeon_pixmap)); 761 752 if (!priv) 762 753 return FALSE; 763 754 } 764 755 765 radeon_b o_ref(bo);756 radeon_buffer_ref(bo); 766 757 priv->bo = bo; 767 768 radeon_bo_get_tiling(bo, &priv->tiling_flags, &pitch);769 758 } 770 759 771 760 radeon_set_pixmap_private(pPix, priv); 761 radeon_get_pixmap_tiling_flags(pPix); 772 762 return TRUE; 773 763 } else 774 764 #endif /* USE_GLAMOR */ … … 779 769 if (driver_priv) { 780 770 uint32_t pitch; 781 771 782 if (driver_priv->bo) 783 radeon_bo_unref(driver_priv->bo); 784 772 radeon_buffer_unref(&driver_priv->bo); 785 773 drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL); 786 774 787 radeon_b o_ref(bo);775 radeon_buffer_ref(bo); 788 776 driver_priv->bo = bo; 789 777 790 radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch); 778 radeon_bo_get_tiling(bo->bo.radeon, &driver_priv->tiling_flags, 779 &pitch); 791 780 return TRUE; 792 781 } 793 782 … … 795 784 } 796 785 } 797 786 798 static inline struct radeon_b o*radeon_get_pixmap_bo(PixmapPtr pPix)787 static inline struct radeon_buffer *radeon_get_pixmap_bo(PixmapPtr pPix) 799 788 { 800 789 #ifdef USE_GLAMOR 801 790 RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen)); … … 905 894 return *fb_ptr; 906 895 } 907 896 897 908 898 #define CP_PACKET0(reg, n) \ 909 899 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 910 900 #define CP_PACKET1(reg0, reg1) \ … … 1013 1003 #define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \ 1014 1004 driver_priv = exaGetPixmapDriverPrivate(pPix); \ 1015 1005 OUT_RING_REG((reg), (value)); \ 1016 OUT_RING_RELOC(driver_priv->bo , (rd), (wd));\1006 OUT_RING_RELOC(driver_priv->bo->bo.radeon, (rd), (wd)); \ 1017 1007 } while(0) 1018 1008 1019 1009 #define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0) … … 1027 1017 #define EMIT_COLORPITCH(reg, value, pPix) do { \ 1028 1018 driver_priv = exaGetPixmapDriverPrivate(pPix); \ 1029 1019 OUT_RING_REG((reg), value); \ 1030 OUT_RING_RELOC(driver_priv->bo , 0, RADEON_GEM_DOMAIN_VRAM);\1020 OUT_RING_RELOC(driver_priv->bo->bo.radeon, 0, RADEON_GEM_DOMAIN_VRAM); \ 1031 1021 } while(0) 1032 1022 1033 1023 static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_kms.c xf86-video-ati-18.0.1/src/radeon_kms.c
old new 212 212 info->accel_state = NULL; 213 213 } 214 214 215 #ifdef USE_GLAMOR 216 if (info->gbm) 217 gbm_device_destroy(info->gbm); 218 #endif 219 215 220 pEnt = info->pEnt; 216 221 free(pScrn->driverPrivate); 217 222 pScrn->driverPrivate = NULL; … … 254 259 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 255 260 *size = stride; 256 261 257 return ((uint8_t *)info->front_b o->ptr + row * stride + offset);262 return ((uint8_t *)info->front_buffer->bo.radeon->ptr + row * stride + offset); 258 263 } 259 264 260 265 static void … … 326 331 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 327 332 RADEONInfoPtr info = RADEONPTR(pScrn); 328 333 PixmapPtr pixmap; 329 struct radeon_surface *surface;330 334 331 335 pScreen->CreateScreenResources = info->CreateScreenResources; 332 336 if (!(*pScreen->CreateScreenResources)(pScreen)) … … 360 364 } 361 365 362 366 if (info->dri2.enabled || info->use_glamor) { 363 if (info->front_b o) {367 if (info->front_buffer) { 364 368 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 365 if (!radeon_set_pixmap_bo(pPix, info->front_b o))369 if (!radeon_set_pixmap_bo(pPix, info->front_buffer)) 366 370 return FALSE; 367 surface = radeon_get_pixmap_surface(pPix); 368 if (surface) { 369 *surface = info->front_surface; 370 } 371 372 if (info->surf_man && !info->use_glamor) 373 *radeon_get_pixmap_surface(pPix) = info->front_surface; 371 374 } 372 375 } 373 376 … … 523 526 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 524 527 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 525 528 526 drmmode_crtc->scanout_update_pending = FALSE;529 drmmode_crtc->scanout_update_pending = 0; 527 530 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 528 531 NULL); 529 532 } … … 538 541 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, 539 542 drmmode_crtc->flip_pending); 540 543 radeon_scanout_flip_abort(crtc, event_data); 541 542 #ifdef HAVE_PRESENT_H543 if (drmmode_crtc->present_vblank_event_id) {544 present_event_notify(drmmode_crtc->present_vblank_event_id,545 drmmode_crtc->present_vblank_usec,546 drmmode_crtc->present_vblank_msc);547 drmmode_crtc->present_vblank_event_id = 0;548 }549 #endif550 544 } 551 545 552 546 … … 608 602 { 609 603 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 610 604 611 drmmode_crtc->scanout_update_pending = FALSE;605 drmmode_crtc->scanout_update_pending = 0; 612 606 } 613 607 614 608 void … … 636 630 { 637 631 ScreenPtr master_screen = radeon_dirty_master(dirty); 638 632 639 return master_screen->SyncSharedPixmap != NULL;633 return !!master_screen->SyncSharedPixmap; 640 634 } 641 635 642 636 static Bool … … 644 638 { 645 639 ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen; 646 640 647 return slave_screen->SyncSharedPixmap != NULL;641 return !!slave_screen->SyncSharedPixmap; 648 642 } 649 643 650 644 static void … … 749 743 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 750 744 751 745 radeon_prime_scanout_do_update(crtc, 0); 752 drmmode_crtc->scanout_update_pending = FALSE;746 drmmode_crtc->scanout_update_pending = 0; 753 747 } 754 748 755 749 static void … … 790 784 return; 791 785 } 792 786 793 drmmode_crtc->scanout_update_pending = TRUE;787 drmmode_crtc->scanout_update_pending = drm_queue_seq; 794 788 } 795 789 796 790 static void … … 848 842 } 849 843 850 844 drmmode_crtc->scanout_id = scanout_id; 851 drmmode_crtc->scanout_update_pending = TRUE;845 drmmode_crtc->scanout_update_pending = drm_queue_seq; 852 846 } 853 847 854 848 static void … … 987 981 FreeScratchGC(gc); 988 982 } 989 983 990 radeon_cs_flush_indirect(scrn);991 992 984 info->accel_state->force = force; 993 985 994 986 return TRUE; … … 999 991 { 1000 992 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1001 993 1002 drmmode_crtc->scanout_update_pending = FALSE;994 drmmode_crtc->scanout_update_pending = 0; 1003 995 } 1004 996 1005 997 static void … … 1015 1007 drmmode_crtc->dpms_mode == DPMSModeOn) { 1016 1008 if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id, 1017 1009 screen->GetWindowPixmap(screen->root), 1018 region->extents)) 1010 region->extents)) { 1011 radeon_cs_flush_indirect(crtc->scrn); 1019 1012 RegionEmpty(region); 1013 } 1020 1014 } 1021 1015 1022 1016 radeon_scanout_update_abort(crtc, event_data); … … 1074 1068 return; 1075 1069 } 1076 1070 1077 drmmode_crtc->scanout_update_pending = TRUE;1071 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1078 1072 } 1079 1073 1080 1074 static void … … 1098 1092 pScreen->GetWindowPixmap(pScreen->root), 1099 1093 region->extents)) 1100 1094 return; 1095 1096 radeon_cs_flush_indirect(scrn); 1101 1097 RegionEmpty(region); 1102 1098 1103 1099 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, … … 1139 1135 } 1140 1136 1141 1137 drmmode_crtc->scanout_id = scanout_id; 1142 drmmode_crtc->scanout_update_pending = TRUE;1138 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1143 1139 } 1144 1140 1145 1141 static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) … … 1162 1158 xf86CrtcPtr crtc = xf86_config->crtc[c]; 1163 1159 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 1164 1160 1161 if (drmmode_crtc->rotate.pixmap) 1162 continue; 1163 1165 1164 if (drmmode_crtc->tear_free) 1166 1165 radeon_scanout_flip(pScreen, info, crtc); 1167 1166 else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) … … 1681 1680 pScreen->WindowExposures(pWin, pRegion); 1682 1681 #endif 1683 1682 1684 radeon_cs_flush_indirect(pScrn); 1685 radeon_bo_wait(info->front_bo); 1683 radeon_finish(pScrn, info->front_buffer); 1686 1684 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); 1687 1685 } 1688 1686 … … 1762 1760 info->dri2.available = FALSE; 1763 1761 info->dri2.enabled = FALSE; 1764 1762 info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd); 1765 if ( info->dri2.pKernelDRMVersion == NULL) {1763 if (!info->dri2.pKernelDRMVersion) { 1766 1764 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1767 1765 "RADEONDRIGetVersion failed to get the DRM version\n"); 1768 1766 return FALSE; … … 1782 1780 return FALSE; 1783 1781 } 1784 1782 1785 radeon_drm_queue_init( );1783 radeon_drm_queue_init(pScrn); 1786 1784 1787 1785 info->allowColorTiling2D = FALSE; 1788 1786 … … 1917 1915 xf86OutputPtr output = xf86_config->output[i]; 1918 1916 1919 1917 /* XXX: double check crtc mode */ 1920 if ( (output->probed_modes != NULL) && (output->crtc == NULL))1918 if (output->probed_modes && !output->crtc) 1921 1919 output->crtc = xf86_config->crtc[0]; 1922 1920 } 1923 1921 } … … 1980 1978 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 1981 1979 } 1982 1980 1983 if ( pScrn->modes == NULL1981 if (!pScrn->modes 1984 1982 #ifdef XSERVER_PLATFORM_BUS 1985 1983 && !pScrn->is_gpu 1986 1984 #endif … … 2091 2089 unblank = xf86IsUnblank(mode); 2092 2090 if (unblank) SetTimeSinceLastInputEvent(); 2093 2091 2094 if ( (pScrn != NULL)&& pScrn->vtSema) {2092 if (pScrn && pScrn->vtSema) { 2095 2093 if (unblank) 2096 2094 RADEONUnblank(pScrn); 2097 2095 else … … 2228 2226 if (info->r600_shadow_fb == FALSE) 2229 2227 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 2230 2228 2231 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd); 2229 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2230 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd); 2231 2232 if (!info->surf_man) { 2233 xf86DrvMsg(pScreen->myNum, X_ERROR, 2234 "Failed to initialize surface manager\n"); 2235 return FALSE; 2236 } 2237 } 2238 2232 2239 if (!info->bufmgr) 2233 2240 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd); 2234 2241 if (!info->bufmgr) { … … 2261 2268 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 2262 2269 return FALSE; 2263 2270 } 2264 front_ptr = info->front_bo->ptr; 2271 2272 if (!(info->front_buffer->flags & RADEON_BO_FLAGS_GBM)) 2273 front_ptr = info->front_buffer->bo.radeon->ptr; 2274 else 2275 front_ptr = NULL; 2265 2276 2266 2277 if (info->r600_shadow_fb) { 2267 2278 info->fb_shadow = calloc(1, 2268 2279 pScrn->displayWidth * pScrn->virtualY * 2269 2280 ((pScrn->bitsPerPixel + 7) >> 3)); 2270 if ( info->fb_shadow == NULL) {2281 if (!info->fb_shadow) { 2271 2282 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2272 2283 "Failed to allocate shadow framebuffer\n"); 2273 2284 return FALSE; … … 2470 2481 if (info->r600_shadow_fb) { 2471 2482 int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0); 2472 2483 struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0, 2473 info->front_bo->size, 2484 pScrn->displayWidth * 2485 info->pixel_bytes * 2486 pScrn->virtualY, 2474 2487 base_align, 2475 2488 RADEON_GEM_DOMAIN_VRAM, 0); 2476 2489 2477 2490 if (front_bo) { 2478 2491 if (radeon_bo_map(front_bo, 1) == 0) { 2479 2492 memset(front_bo->ptr, 0, front_bo->size); 2480 radeon_bo_unref(info->front_b o);2481 info->front_b o= front_bo;2493 radeon_bo_unref(info->front_buffer->bo.radeon); 2494 info->front_buffer->bo.radeon = front_bo; 2482 2495 } else { 2483 2496 radeon_bo_unref(front_bo); 2484 2497 front_bo = NULL; … … 2576 2589 radeon_pixmap_get_fb(black_scanout.pixmap); 2577 2590 2578 2591 radeon_pixmap_clear(black_scanout.pixmap); 2579 radeon_cs_flush_indirect(pScrn); 2580 radeon_bo_wait(black_scanout.bo); 2592 radeon_finish(pScrn, black_scanout.bo); 2581 2593 2582 2594 for (i = 0; i < xf86_config->num_crtc; i++) { 2583 2595 crtc = xf86_config->crtc[i]; … … 2626 2638 2627 2639 pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen), None, pRADEONEnt); 2628 2640 } else { 2629 memset(info->front_bo->ptr, 0, info->front_bo->size); 2641 memset(info->front_buffer->bo.radeon->ptr, 0, 2642 pScrn->displayWidth * info->pixel_bytes * pScrn->virtualY); 2630 2643 } 2631 2644 2632 2645 TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen); … … 2664 2677 RADEONInfoPtr info = RADEONPTR(pScrn); 2665 2678 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2666 2679 int cpp = info->pixel_bytes; 2667 uint32_t screen_size; 2668 int pitch, base_align; 2680 int pitch; 2669 2681 uint32_t tiling_flags = 0; 2670 struct radeon_surface surface;2671 2682 2672 if (info->accel_state->exa != NULL) {2683 if (info->accel_state->exa) { 2673 2684 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 2674 2685 return FALSE; 2675 2686 } 2676 2687 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 2677 2688 info->accel_state->exa = exaDriverAlloc(); 2678 if ( info->accel_state->exa == NULL) {2689 if (!info->accel_state->exa) { 2679 2690 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 2680 2691 return FALSE; 2681 2692 } 2682 2693 } 2683 2694 2684 if (info->allowColorTiling && !info->shadow_primary) {2685 if (info->ChipFamily >= CHIP_FAMILY_R600) {2686 if (info->allowColorTiling2D) {2687 tiling_flags |= RADEON_TILING_MACRO;2688 } else {2689 tiling_flags |= RADEON_TILING_MICRO;2690 }2691 } else2692 tiling_flags |= RADEON_TILING_MACRO;2693 }2694 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;2695 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;2696 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);2697 if (info->ChipFamily >= CHIP_FAMILY_R600) {2698 if(!info->surf_man) {2699 xf86DrvMsg(pScreen->myNum, X_ERROR,2700 "failed to initialise surface manager\n");2701 return FALSE;2702 }2703 memset(&surface, 0, sizeof(struct radeon_surface));2704 surface.npix_x = pScrn->virtualX;2705 surface.npix_y = pScrn->virtualY;2706 surface.npix_z = 1;2707 surface.blk_w = 1;2708 surface.blk_h = 1;2709 surface.blk_d = 1;2710 surface.array_size = 1;2711 surface.last_level = 0;2712 surface.bpe = cpp;2713 surface.nsamples = 1;2714 surface.flags = RADEON_SURF_SCANOUT;2715 /* we are requiring a recent enough libdrm version */2716 surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;2717 surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);2718 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);2719 if (tiling_flags & RADEON_TILING_MICRO) {2720 surface.flags = RADEON_SURF_CLR(surface.flags, MODE);2721 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);2722 }2723 if (tiling_flags & RADEON_TILING_MACRO) {2724 surface.flags = RADEON_SURF_CLR(surface.flags, MODE);2725 surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);2726 }2727 if (radeon_surface_best(info->surf_man, &surface)) {2728 xf86DrvMsg(pScreen->myNum, X_ERROR,2729 "radeon_surface_best failed\n");2730 return FALSE;2731 }2732 if (radeon_surface_init(info->surf_man, &surface)) {2733 xf86DrvMsg(pScreen->myNum, X_ERROR,2734 "radeon_surface_init failed\n");2735 return FALSE;2736 }2737 pitch = surface.level[0].pitch_bytes;2738 screen_size = surface.bo_size;2739 base_align = surface.bo_alignment;2740 tiling_flags = 0;2741 switch (surface.level[0].mode) {2742 case RADEON_SURF_MODE_2D:2743 tiling_flags |= RADEON_TILING_MACRO;2744 tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;2745 tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;2746 tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;2747 if (surface.tile_split)2748 tiling_flags |= eg_tile_split(surface.tile_split)2749 << RADEON_TILING_EG_TILE_SPLIT_SHIFT;2750 break;2751 case RADEON_SURF_MODE_1D:2752 tiling_flags |= RADEON_TILING_MICRO;2753 break;2754 default:2755 break;2756 }2757 info->front_surface = surface;2758 }2759 2695 { 2760 2696 int cursor_size; 2761 2697 int c; … … 2764 2700 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 2765 2701 for (c = 0; c < xf86_config->num_crtc; c++) { 2766 2702 /* cursor objects */ 2767 if ( info->cursor_bo[c] == NULL) {2703 if (!info->cursor_bo[c]) { 2768 2704 info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0, 2769 2705 cursor_size, 0, 2770 2706 RADEON_GEM_DOMAIN_VRAM, 0); … … 2782 2718 } 2783 2719 } 2784 2720 2785 screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE); 2721 if (!info->front_buffer) { 2722 int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP; 2723 2724 if (info->allowColorTiling && !info->shadow_primary) { 2725 if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D) 2726 usage |= RADEON_CREATE_PIXMAP_TILING_MACRO; 2727 else 2728 usage |= RADEON_CREATE_PIXMAP_TILING_MICRO; 2729 } 2730 2731 info->front_buffer = radeon_alloc_pixmap_bo(pScrn, pScrn->virtualX, 2732 pScrn->virtualY, 2733 pScrn->depth, 2734 usage, 2735 pScrn->bitsPerPixel, 2736 &pitch, 2737 &info->front_surface, 2738 &tiling_flags); 2786 2739 2787 if (info->front_bo == NULL) {2788 info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,2789 base_align,2790 info->shadow_primary ?2791 RADEON_GEM_DOMAIN_GTT :2792 RADEON_GEM_DOMAIN_VRAM,2793 tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0);2794 2740 if (info->r600_shadow_fb == TRUE) { 2795 if (radeon_bo_map(info->front_b o, 1)) {2741 if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) { 2796 2742 ErrorF("Failed to map cursor buffer memory\n"); 2797 2743 } 2798 2744 } 2745 2746 if (!info->use_glamor) { 2799 2747 #if X_BYTE_ORDER == X_BIG_ENDIAN 2800 switch (cpp) {2801 case 4:2802 2803 2804 case 2:2805 2806 2807 }2808 if (info->ChipFamily < CHIP_FAMILY_R600 &&2809 2810 2748 switch (cpp) { 2749 case 4: 2750 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2751 break; 2752 case 2: 2753 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2754 break; 2755 } 2756 if (info->ChipFamily < CHIP_FAMILY_R600 && 2757 info->r600_shadow_fb && tiling_flags) 2758 tiling_flags |= RADEON_TILING_SURFACE; 2811 2759 #endif 2812 if (tiling_flags) 2813 radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch); 2760 if (tiling_flags) 2761 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch); 2762 } 2814 2763 } 2815 2764 2816 2765 pScrn->displayWidth = pitch / cpp; 2817 2766 2818 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024); 2819 radeon_kms_update_vram_limit(pScrn, screen_size); 2767 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", 2768 pitch * pScrn->virtualY / 1024); 2769 radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY); 2820 2770 return TRUE; 2821 2771 } 2822 2772 … … 2828 2778 int c; 2829 2779 2830 2780 for (c = 0; c < xf86_config->num_crtc; c++) { 2831 if (info->cursor_bo[c] != NULL) {2781 if (info->cursor_bo[c]) 2832 2782 new_fb_size += (64 * 4 * 64); 2833 }2834 2783 } 2835 2784 2836 2785 remain_size_bytes = info->vram_size - new_fb_size; -
src/radeon_present.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_present.c xf86-video-ati-18.0.1/src/radeon_present.c
old new 52 52 53 53 struct radeon_present_vblank_event { 54 54 uint64_t event_id; 55 Bool vblank_for_flip;56 55 Bool unflip; 57 56 }; 58 57 … … 110 109 if (r <= 0) 111 110 return 0; 112 111 113 return drmHandleEvent(pRADEONEnt->fd, &drmmode->event_context) >= 0;112 return radeon_drm_handle_event(pRADEONEnt->fd, &drmmode->event_context) >= 0; 114 113 } 115 114 116 115 /* … … 120 119 radeon_present_vblank_handler(xf86CrtcPtr crtc, unsigned int msc, 121 120 uint64_t usec, void *data) 122 121 { 123 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;124 122 struct radeon_present_vblank_event *event = data; 125 123 126 if (event->vblank_for_flip && 127 drmmode_crtc->tear_free && 128 drmmode_crtc->scanout_update_pending) { 129 if (drmmode_crtc->present_vblank_event_id != 0) { 130 xf86DrvMsg(crtc->scrn->scrnIndex, X_WARNING, 131 "Need to handle previously deferred vblank event\n"); 132 present_event_notify(drmmode_crtc->present_vblank_event_id, 133 drmmode_crtc->present_vblank_usec, 134 drmmode_crtc->present_vblank_msc); 135 } 136 137 drmmode_crtc->present_vblank_event_id = event->event_id; 138 drmmode_crtc->present_vblank_msc = msc; 139 drmmode_crtc->present_vblank_usec = usec; 140 } else 141 present_event_notify(event->event_id, usec, msc); 142 124 present_event_notify(event->event_id, usec, msc); 143 125 free(event); 144 126 } 145 127 … … 162 144 radeon_present_queue_vblank(RRCrtcPtr crtc, uint64_t event_id, uint64_t msc) 163 145 { 164 146 xf86CrtcPtr xf86_crtc = crtc->devPrivate; 165 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;166 147 ScreenPtr screen = crtc->pScreen; 167 148 struct radeon_present_vblank_event *event; 168 149 uintptr_t drm_queue_seq; … … 171 152 if (!event) 172 153 return BadAlloc; 173 154 event->event_id = event_id; 174 event->vblank_for_flip = drmmode_crtc->present_flip_expected;175 drmmode_crtc->present_flip_expected = FALSE;176 155 177 156 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 178 157 RADEON_DRM_QUEUE_CLIENT_DEFAULT, … … 272 251 Bool sync_flip) 273 252 { 274 253 xf86CrtcPtr xf86_crtc = crtc->devPrivate; 275 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;276 254 ScreenPtr screen = window->drawable.pScreen; 277 255 ScrnInfoPtr scrn = xf86_crtc->scrn; 278 256 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); … … 281 259 int num_crtcs_on; 282 260 int i; 283 261 284 drmmode_crtc->present_flip_expected = FALSE;285 286 262 if (!scrn->vtSema) 287 263 return FALSE; 288 264 … … 313 289 if (num_crtcs_on == 0) 314 290 return FALSE; 315 291 316 drmmode_crtc->present_flip_expected = TRUE;317 292 return TRUE; 318 293 } 319 294 … … 354 329 PixmapPtr pixmap, Bool sync_flip) 355 330 { 356 331 xf86CrtcPtr xf86_crtc = crtc->devPrivate; 357 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;358 332 ScreenPtr screen = crtc->pScreen; 359 333 ScrnInfoPtr scrn = xf86_crtc->scrn; 360 334 RADEONInfoPtr info = RADEONPTR(scrn); … … 362 336 Bool ret = FALSE; 363 337 364 338 if (!radeon_present_check_flip(crtc, screen->root, pixmap, sync_flip)) 365 goto out;339 return ret; 366 340 367 341 event = calloc(1, sizeof(struct radeon_present_vblank_event)); 368 342 if (!event) 369 goto out;343 return ret; 370 344 371 345 event->event_id = event_id; 372 346 … … 383 357 else 384 358 info->drmmode.present_flipping = TRUE; 385 359 386 out:387 drmmode_crtc->present_flip_expected = FALSE;388 360 return ret; 389 361 } 390 362 … … 404 376 FLIP_ASYNC : FLIP_VSYNC; 405 377 int i; 406 378 407 radeon_cs_flush_indirect(scrn);408 409 379 if (!radeon_present_check_unflip(scrn)) 410 380 goto modeset; 411 381 … … 424 394 return; 425 395 426 396 modeset: 427 radeon_ bo_wait(info->front_bo);397 radeon_finish(scrn, info->front_buffer); 428 398 for (i = 0; i < config->num_crtc; i++) { 429 399 xf86CrtcPtr crtc = config->crtc[i]; 430 400 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_probe.c xf86-video-ati-18.0.1/src/radeon_probe.c
old new 278 278 } 279 279 #endif 280 280 281 _X_EXPORTDriverRec RADEON =281 DriverRec RADEON = 282 282 { 283 283 RADEON_VERSION_CURRENT, 284 284 RADEON_DRIVER_NAME, -
src/radeon_textured_video.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_textured_video.c xf86-video-ati-18.0.1/src/radeon_textured_video.c
old new 153 153 static void 154 154 RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) 155 155 { 156 if (pPriv->video_memory != NULL) {156 if (pPriv->video_memory) { 157 157 radeon_bo_unref(pPriv->video_memory); 158 158 pPriv->video_memory = NULL; 159 159 … … 312 312 RADEONFreeVideoMemory(pScrn, pPriv); 313 313 } 314 314 315 if ( pPriv->video_memory == NULL) {315 if (!pPriv->video_memory) { 316 316 Bool ret; 317 317 ret = radeon_allocate_video_bo(pScrn, 318 318 &pPriv->video_memory, … … 329 329 330 330 /* Bicubic filter loading */ 331 331 if (pPriv->bicubic_enabled) { 332 if ( info->bicubic_bo == NULL)332 if (!info->bicubic_bo) 333 333 pPriv->bicubic_enabled = FALSE; 334 334 } 335 335 … … 725 725 { 726 726 RADEONInfoPtr info = RADEONPTR(pScrn); 727 727 728 if (info->bicubic_memory != NULL) {728 if (info->bicubic_memory) { 729 729 radeon_bo_unref(info->bicubic_memory); 730 730 info->bicubic_memory = NULL; 731 731 } … … 827 827 828 828 adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports * 829 829 (sizeof(RADEONPortPrivRec) + sizeof(DevUnion))); 830 if ( adapt == NULL)830 if (!adapt) 831 831 return NULL; 832 832 833 833 xvBicubic = MAKE_ATOM("XV_BICUBIC"); -
src/radeon_textured_videofuncs.c
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_textured_videofuncs.c xf86-video-ati-18.0.1/src/radeon_textured_videofuncs.c
old new 63 63 radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 64 64 65 65 if (pPriv->bicubic_enabled) 66 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 66 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, 67 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 67 68 68 69 driver_priv = exaGetPixmapDriverPrivate(pPixmap); 69 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); 70 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 71 RADEON_GEM_DOMAIN_VRAM); 70 72 71 73 ret = radeon_cs_space_check(info->cs); 72 74 if (ret) { … … 433 435 radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 434 436 435 437 if (pPriv->bicubic_enabled) 436 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 438 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, 439 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 437 440 438 441 driver_priv = exaGetPixmapDriverPrivate(pPixmap); 439 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); 442 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 443 RADEON_GEM_DOMAIN_VRAM); 440 444 441 445 ret = radeon_cs_space_check(info->cs); 442 446 if (ret) { … … 958 962 radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 959 963 960 964 if (pPriv->bicubic_enabled) 961 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 965 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, 966 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 962 967 963 968 driver_priv = exaGetPixmapDriverPrivate(pPixmap); 964 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); 969 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 970 RADEON_GEM_DOMAIN_VRAM); 965 971 966 972 ret = radeon_cs_space_check(info->cs); 967 973 if (ret) { … … 2376 2382 radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 2377 2383 2378 2384 if (pPriv->bicubic_enabled) 2379 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 2385 radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, 2386 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); 2380 2387 2381 2388 driver_priv = exaGetPixmapDriverPrivate(pPixmap); 2382 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); 2389 radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo->bo.radeon, 0, 2390 RADEON_GEM_DOMAIN_VRAM); 2383 2391 2384 2392 ret = radeon_cs_space_check(info->cs); 2385 2393 if (ret) { -
xf86-video-ati-18.0.1
diff -Naur xf86-video-ati-18.0.1.orig/src/radeon_video.c xf86-video-ati-18.0.1/src/radeon_video.c
old new 144 144 145 145 num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors); 146 146 newAdaptors = malloc((num_adaptors + 2) * sizeof(*newAdaptors)); 147 if ( newAdaptors == NULL)147 if (!newAdaptors) 148 148 return; 149 149 150 150 memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); … … 152 152 153 153 if (info->use_glamor) { 154 154 texturedAdaptor = radeon_glamor_xv_init(pScreen, 16); 155 if (texturedAdaptor != NULL) {155 if (texturedAdaptor) { 156 156 adaptors[num_adaptors++] = texturedAdaptor; 157 157 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video (glamor)\n"); 158 158 } else … … 161 161 || (info->directRenderingEnabled) 162 162 ) { 163 163 texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); 164 if (texturedAdaptor != NULL) {164 if (texturedAdaptor) { 165 165 adaptors[num_adaptors++] = texturedAdaptor; 166 166 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); 167 167 } else